ESA Microelectronics Section

Papers and internal Research Reports


This page presents various papers, trainee and YGT reports.


Report   DescriptionAuthor/Date      
DAC-2013Single Event Upset Hardening by 'hijacking' the multi-VT flow during synthesisRoland Weigand, June 2013
Navitec-2012Next generation of ESA's GNSS receivers for Earth Observation satellitesJosep Rosello, Pierluigi Silvestrin, Roland Weigand, Salvatore d'Addio, Alberto Garcia Rodriguez, Gustavo Lopez Risueno, December 2012
FlightSoftwareWorkshop2012Current and Next Generation LEON System-On-Chip Architectures for Space (slides)Jan Andersson, Daniel Hellstrom, Sandi Habinc, Roland Weigand, Luca Fossati, October 2012
DASIA-2012Advanced GPS Galileo ASIC (AGGA-4) - Enabling Next Generation of Navigation ReceiversM. Syed, I. Tejerina, J. Heim (Astrium Germany), J. Rosello, R. Weigand, May 2012
DASIA-2011ESA Microprocessor Development - Status and Roadmap (slides)Roland Weigand, May 2011
Navitec-2010AGGA-4: core device for GNSS space receivers of this decade (slides) Josep Rosello, Pierluigi Silvestrin, Gustavo Lopez Risueno, R. Weigand, J.V. Perello, Jens Heim, Isaac Tejerina, December 2010
Ka-Band Conference 2010Next generation of miniaturised receivers with new GNSS signalsJ. Rosello, P. Silvestrin , G. Lopez Risueno, Ville Kangas, Roland Weigand, September 2010
DASIA-2010Next Generation Multi-Purpose MicroprocessorJan Andersson, Magnus Sjalander, Jiri Gaisler, Roland Weigand, May 2010
DAC2009Design of a Single Event Effect fault tolerant microprocessor for space using mainstream commercial EDA tools (slides)Roland Weigand, Jean Edelin (Atmel), July 2009
DSNOC2009Single Event Effects in SRAM based FPGA for space applications, presentation at Diagnostic Services in Network-on-Chips workshop (collocated with DATE)Roland Weigand, April 2009
Navitec-2008AGGA-4: Core device for GNSS space-receivers of the next decadeJ. Rosello Guasch, R. Weigand, G. Lopez Risueno, P. Silvestrin, December 2008
TWEPP-2010Single Event Effect Mitigation in Digital Integrated Circuits for SpaceRoland Weigand, Sep. 2010
Susanna, Jonathan, PurpleDesign-dependent reliability tools and layout tools improvement for Atmel FPGAFilomena Decuzzi, May 2010
InFaultSmart Behavioural Netlist Simulation for SEU Protection VerificationSimon Schulz, Giovanni Beltrame, David Merodio Codinachs, RADECS 2008
Pilar-2008System Knowledge Based Protection Techniques Against SEEs Caused by Space Radiation for Fast Fourier TransformsPilar Reyes Moreno, January 2008
SCOC3-DASIA2007Presentation of the SCOC3 ASIC at DAta Systems In Aerospace (DASIA) conference (abstract)May 2007
OCP: Open Core ProtocolAn ESA internal case study, converting the CAN IP core to OCPMarta Posada, June 2006
SEE Analysis and MitigationSEE Analysis and Mitigation for FPGA and Digital ASIC Devices, presentation held at the IEE Seminar on Cosmic Radiation and University of SurreyRoland Weigand, December 2005
Magillem SOC DevelopmentSystem On Chip Development Based on Magillem 2.3SEMattias Carlqvist, December 2005
SystemC MethodologyResearch on New Design Methodology using SystemCNicolas Lainé, August 2005
80S32 BoardSpecification of a Validation Board for the 80S32 8-bit MicrocontrollerSami Heinisuo, May 2003
GalileoSimThe objective of the activity was to develop a signal generator for GALILEO and GPS signals. At first, a software signal generator was implemented in Matlab. The software signal generator has to serve to rapidly prototype different transmitter configurations, algorithms and techniques, assess the performance of GALILEO signals, and create initial designs for further hardware implementations. Then, the signal generator was ported to VHDL code. A hardware implementation, e.g. on FPGA, will introduce higher efficiency due to its higher processing speed, allowing real-time generation of the signal.Juan Jose Borras Aguilar, YGT at ESTEC, January 2003
TTC01Authentication in the Telecommand Link to Improve Security (viewgraphs)ESA/ESTEC TOS-ESM internal study, 2001
PDFEA Particle Detector Front-End ASICdiverse from ESA and IMEC, ESCCON 2000
PCI-AMBAPCI Core - AMBA Bus interfaceElsa Lama Vaquero, Nov. 2000
PCI-AnnexAdditional documentation on the PCI core developed by R. LocatelliElsa Lama Vaquero, March 2000
PCI-CoreDevelopment of a Master/Target PCI VHDL CoreRiccardo Locatelli, Sep. 1999
CSD-FilterBankASIC Implementation of a Filter Bank Analyzer Based on CSD CodeChristian Rosadini, Sept. 1999
ACS & FFTYGT Report in 2 parts: Digital Autocorrelation Spectrometers for Space-Borne Applications and Design of a Parallel FFT Processor Using Fixed Point Arithmetic and CSD MultiplicationRoland Weigand, YGT at ESTEC, August 1995


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Last edited Fri Aug 25 14:30:46 2017