| Report | Description | Author/Date |
| RISC-V-EuropeanSummit | RISC-V - a Rising Star in Space -- Keynote Presentation | Roland Weigand, June 2023
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| ADCSS-21-RISCV | RISC-V: first steps into space Presentation Video (452 MB) | Roland Weigand (ESA), Nov 2021
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| ADCSS-21-GOMX5 | GOMX5 Advanced P/L including new European space components Presentation Video (675 MB) | Arne Samuelsson (Cobham Gaisler), Artur Kobylkiewicz (GMV), Eduardo Augusto Bezerra (UFSC), Roman Wawrzaszek (CBK), Nov 2021
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| ADCSS-19-OpenSourceISA | Open Instruction Set Architectures (ISA) in Space | Roland Weigand, November 2019
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| DAC-2013 | Single Event Upset Hardening by 'hijacking' the multi-VT flow during synthesis | Roland Weigand, June 2013
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| Navitec-2012 | Next generation of ESA's GNSS receivers for Earth Observation satellites | Josep Rosello, Pierluigi Silvestrin, Roland Weigand, Salvatore d'Addio, Alberto Garcia Rodriguez, Gustavo Lopez Risueno, December 2012
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| FlightSoftwareWorkshop2012 | Current and Next Generation LEON System-On-Chip Architectures for Space (slides) | Jan Andersson, Daniel Hellstrom, Sandi Habinc, Roland Weigand, Luca Fossati, October 2012
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| DASIA-2012 | Advanced GPS Galileo ASIC (AGGA-4) - Enabling Next Generation of Navigation Receivers | M. Syed, I. Tejerina, J. Heim (Astrium Germany), J. Rosello, R. Weigand, May 2012
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| DASIA-2011 | ESA Microprocessor Development - Status and Roadmap (slides) | Roland Weigand, May 2011
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| Navitec-2010 | AGGA-4: core device for GNSS space receivers of this decade (slides) | Josep Rosello, Pierluigi Silvestrin, Gustavo Lopez Risueno, R. Weigand, J.V. Perello, Jens Heim, Isaac Tejerina, December 2010
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| Ka-Band Conference 2010 | Next generation of miniaturised receivers with new GNSS signals | J. Rosello, P. Silvestrin , G. Lopez Risueno, Ville Kangas, Roland Weigand, September 2010
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| DASIA-2010 | Next Generation Multi-Purpose Microprocessor | Jan Andersson, Magnus Sjalander, Jiri Gaisler, Roland Weigand, May 2010
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| DAC2009 | Design of a Single Event Effect fault tolerant microprocessor for space using mainstream commercial EDA tools (slides) | Roland Weigand, Jean Edelin (Atmel), July 2009
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| DSNOC2009 | Single Event Effects in SRAM based FPGA for space applications, presentation at Diagnostic Services in Network-on-Chips workshop (collocated with DATE) | Roland Weigand, April 2009
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| Navitec-2008 | AGGA-4: Core device for GNSS space-receivers of the next decade | J. Rosello Guasch, R. Weigand, G. Lopez Risueno, P. Silvestrin, December 2008
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| TWEPP-2010 | Single Event Effect Mitigation in Digital Integrated Circuits for Space | Roland Weigand, Sep. 2010
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| Susanna, Jonathan, Purple | Design-dependent reliability tools and layout tools improvement for Atmel FPGA | Filomena Decuzzi, May 2010
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| InFault | Smart Behavioural Netlist Simulation for SEU Protection Verification | Simon Schulz, Giovanni Beltrame, David Merodio Codinachs, RADECS 2008
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| Pilar-2008 | System Knowledge Based Protection Techniques Against SEEs Caused by Space Radiation for Fast Fourier Transforms | Pilar Reyes Moreno, January 2008
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| SCOC3-DASIA2007 | Presentation of the SCOC3 ASIC at DAta Systems In Aerospace (DASIA) conference (abstract) | May 2007
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| OCP: Open Core Protocol | An ESA internal case study, converting the CAN IP core to OCP | Marta Posada, June 2006
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| SEE Analysis and Mitigation | SEE Analysis and Mitigation for FPGA and Digital ASIC Devices, presentation held at the IEE Seminar on Cosmic Radiation and University of Surrey | Roland Weigand, December 2005
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| Magillem SOC Development | System On Chip Development Based on Magillem 2.3SE | Mattias Carlqvist, December 2005
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| SystemC Methodology | Research on New Design Methodology using SystemC | Nicolas Lainé, August 2005
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| 80S32 Board | Specification of a Validation Board for the 80S32 8-bit Microcontroller | Sami Heinisuo, May 2003
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| GalileoSim | The objective of the activity was to develop a signal generator for GALILEO and GPS signals. At first, a software signal generator was implemented in Matlab. The software signal generator has to serve to rapidly prototype different transmitter configurations, algorithms and techniques, assess the performance of GALILEO signals, and create initial designs for further hardware implementations. Then, the signal generator was ported to VHDL code. A hardware implementation, e.g. on FPGA, will introduce higher efficiency due to its higher processing speed, allowing real-time generation of the signal. | Juan Jose Borras Aguilar, YGT at ESTEC, January 2003
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| TTC01 | Authentication in the Telecommand Link to Improve Security (viewgraphs) | ESA/ESTEC TOS-ESM internal study, 2001
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| PDFE | A Particle Detector Front-End ASIC | diverse from ESA and IMEC, ESCCON 2000
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| PCI-AMBA | PCI Core - AMBA Bus interface | Elsa Lama Vaquero, Nov. 2000
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| PCI-Annex | Additional documentation on the PCI core developed by R. Locatelli | Elsa Lama Vaquero, March 2000
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| PCI-Core | Development of a Master/Target PCI VHDL Core | Riccardo Locatelli, Sep. 1999
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| CSD-FilterBank | ASIC Implementation of a Filter Bank Analyzer Based on CSD Code | Christian Rosadini, Sept. 1999
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| ACS & FFT | YGT Report in 2 parts: Digital Autocorrelation Spectrometers for Space-Borne Applications and Design of a Parallel FFT Processor Using Fixed Point Arithmetic and CSD Multiplication | Roland Weigand, YGT at ESTEC, August 1995
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