On-Board Components

Due to the announced discontinuation of all SOS4 and SOS5 MITEL (S) products, all related information has been removed from this page. This includes the following components: Virtual Channel Assembler (VCA) MS12399, Virtual Channel Multiplexer (VCM) MS12396, Reed-Solomon and Convolutional Encoder (RESCUE) MS13544, Packet Telecommand Decoder (PTCD) MS13545 and Local Time Management System (LTMS) MS13196. The data sheets for some of the aforementioned components are available in the following repository .

Standard ASIC's (ASSP)

• Control Loop Processor: The CLP is a deterministic microprocessor specialised for hard-real time mechatronics control loops. This ASSP project has completed Preliminary Design Review (PDR) in 2016, the resulting IP core will be used on the Thrust Vector Control of Ariane-6/Vega-C.
• SCOC3 will be the ASIC version of the previous SCOC1 study, featuring the LEON3 processor with GRFPU, TM/TC interfaces, various on-board interfaces (Spacewire, CAN, 1553), time management. The development is entering the Architectural Design phase in Q1/2007.
• AT697E, a 32-bit Sparc V8 microprocessor, based on the LEON2-FT IP core (Validation Report).
• AT697F, a 32-bit Sparc V8 microprocessor, based on the LEON2-FT IP core.
• AGGA3, next generation GNSS baseband ASIC, successor of the AGGA2
• SCTMTC (Users Manual Issue 11, March 2006), Single Chip Telemetry/Telecommand ASIC, successor of the obsolete VCM/VCA chipset
• SMCS-Spacewire, SMCS332-SpW and SMCS116-SpW are upgrades to the Spacewire standard of the existing SMCS chips SMCS332 (Atmel TSS901E) and SMCSLite (Atmel T7906E)
• SpaceWire Remote Terminal Controller (SPW-RTC), an intelligent bridge between the SpaceWire backbone network and CAN, embedding the LEON2-FT microprocessor (announcment on Spacewire website).

  The SPW-RTC has been established as Atmel catalog product ref. AT7913E.

  Pending availability from Atmel, the SPW-RTC User Manual is provided here.

• SpaceWire Router, connecting 8 spacewire ports and two 8-bit FIFO ports (announcement on Spacewire website)

Other ASIC Developments

• LEON(FT)-UMC: The LEON-FT VHDL model is a SEU fault-tolerant SPARC V8 processor developed for future space missions. It has been implemented by ESA on a 0.18 um commercial technology from UMC using the commercial VMC (Virtual Silicon Technologies) libraries. Layout and manufacturing services were provided by IMEC/Europractice. A validation and prototyping board was manufactured by Gaisler Research and Pender Electronic Design, and the chip was SEU tested at ESTEC's Californium facilities. Board and a limited supply of chips are available as advance-prototypes for the upcoming Atmel AT697 component (LEON-FT in 0.18 uym rad-hard technology).
• The IRIS3 CMOS Active Pixel Sensor : As a new member of the Integrated Radiation Tolerant Imaging System (IRIS) family, the IRIS3 sensor has been developed under ESA contract 13716. IRIS3 is a 1024x768 pixel imager, including on-chip sequencing/windowing features, CCSDS packetising, SDRAM interface. It has undergone electrooptical characterisation and radiation tests, demonstrating a total dose hardness up to 30 krad. For further information, please refer to FillFactory.
• AGGA2: The flight version of this GPS/GLONASS baseband processor was designed as an ESA internal project and manufactured as Atmel standard component T7905
• The EVI32 (ERC32 VME-bus Interface) chip T7907E : The EVI32 VHDL core, adapted to work with the ERC32 three chip and single chip processors, as well as the 21020 DSP, has been implemented by Astrium Velizy to the T7907E chip (datasheet) under ESA contract 13345. This chip shall be commercialised by Atmel.
• The ERC32 Microprocessor Family: Documentation on the two ERC32 32-bit Sparc V7 microprocessors (3 chip-set and single-chip) for space applications, developed under ESA programme between 1993 - 1999.
  
• 80S32 (DataSheet): A microcontroller based on the well-known Intel 8052 device has been developed by Transwitch (former ADV Engineering), engineering samples have been produced in Q3/2001 in Atmel MG2-RT technology. The ADV80S32 device has built-in support for CCSDS telecommand and telemetry and targets to applications with moderate processing requirements but needing high safety and easy accommodation of equipment interfaces. Validation of the 80S32 has been performed in 2008/2009 by Integrated Systems Development SA (ISD), resulting in the following dissemination material:
  80S32 Errata Sheet, 80S32 Validation Report, 80S32 Radiation Report

Historical Documentation

CMOS imagers are generally tauted as being particularly suited to the harsh space environment, if only they could get their performance up to CCD levels. This paper highlights present-day high-end CMOS APS sensors from the commercial and industrial world. In addition, the current state of radiation tolerance is discussed. Authors: Sandi Habinc (ESA/ESTEC TOS-ESM), et al.

The PDFE is a low power, low noise mixed analogue-digital CMOS ASIC used  for particle spectroscopy. The ASIC is directly connected to the detector and does all the analogue signal processing up to analogue-to-digital conversion. Authors: Jan Wouters et al. (IMEC), Sandi Habinc (ESA/ESTEC TOS-ESM), Bengt Johlander et al. (ESA/ESTEC SCI-SO).

This paper describes a concept, called dynamical binning, for enhancing the robustness of star trackers to high angular rates. The proposed concept aims to de-spread the star image by over sampling and combining the pixel read-outs from successive sub samples in a manner that compensates for the motion of the star image. Authors: Sandi Habinc (ESA/ESTEC TOS-ESM), Richard Creasey (ESA/ESTEC TOS-ES), et al.

With more than 500 conventional sensors on a medium sized spacecraft there is a substantial application potential for smart sensor technology which is not exploited today. This paper gives an overview of Space applications and the Space infrastructure in place. Current initiatives of the European Space Agency on the development of smart sensor systems for future space missions are presented. Authors: Bernhard Hufenbach (ESA/ESTEC MSM-HP), Sandi Habinc (ESA/ESTEC TOS-ESM) and Pierrik Vuilleumier (ESA/ESTEC TOS-EST).

This paper presents the second generation radiation tolerant Advanced GPS GLONASS ASIC, the AGGA-2, implementing the core digital signal processing for combined GPS and GLONASS receivers. The AGGA-2 supports a wide range of space related applications, both for single-frequency (C/A-code) and dual-frequency (both C/A- and P-code) receivers. The paper describes the principles of GPS operation, followed by a list of applications targeted by the AGGA-2, typical receiver configurations and an overview of the AGGA-2 functionality. Authors: Peter Sinander (ESA/ESTEC TOS-ESM) and Pierluigi Silvestrin (ESA/ESTEC APP-JPP).
The AGGA2 is available as Atmel standard component T7905E. Datasheet: ESA server or Atmel pages

A new coding scheme known as Turbo Coding is being introduced in the telemetry channel coding recommendations from the Consultative Committee for Space Data Systems (CCSDS). As turbo coding is being considered for several European scientific spacecraft, the development of a turbo encoder core and devices, with the associated ground system, has been undertaken by the European Space Agency (ESA). Authors: Sandi Habinc (ESA/ESTEC TOS-ESM), et al.

The PETRA is a mixed analogue/digital device demonstrating a novel concept for retrieving sensor data on-board spacecraft: each PETRA chip can connect up to 40 analogue or digital sensors which are sampled at a nominal period between 10 ms and 50 s. The sensor data is output as CCSDS compliant Telemetry packets. Several PETRA chips can be cascaded in a chain, to be able to connect as many sensors as required. This first demonstrator has been implemented in a commercial non radiation-hard technology from AMS. Author: Dermott MacEvilly (SSL). The complete PETRA Preliminary Data Sheet can be provided upon request .

The Packetised Essential Telemetry Retrieval ASIC (PETRA) is a mixed analogue/digital chip for retrieving sensor data on-board spacecraft. This paper introduces the advantages of using the PETRA in a spacecraft's Data Handling System compared to a traditional implementation. Authors: Debbie Reddy (SSL), Peter Sinander (ESA/ESTEC TOS-ESM), et al.

By applying the packet telemetry and telecommand standards endorsed by the European Space Agency (ESA) and the Consultative Committee for Space Data Systems (CCSDS) to a microcamera, the need for support from the on-board data handling system can almost be eliminated. If the microcamera is designed with interfaces that fully match those of the telemetry and the telecommand subsystem, the additional interface components will be reduced to simple transceivers. Authors: Werner Ogiers (IMEC, Sandi Habinc (ESA/ESTEC TOS-ESM), et al.

The Particle Detector Front End (PDFE) ASIC together with an 8052 based microcontroller forms a chip set being developed by the European Space Agency (ESA) for compact low cost scientific energetic particle instrumentation. Driving requirements of low noise and power consumption led to the selection of a single configurable analogue channel followed by an internal 8-bit ADC. Low mass and volume necessitated for space applications require on-chip integration of supporting functions such as discriminators, independent coincidence event detection and an efficient serial control interface. Authors: Bengt Johlander (ESA/ESTEC SCI-SO), Sandi Habinc and Peter Sinander (ESA/ESTEC TOS-ESM), et al.

Presentation of the 80S32 microcontroller and the LEON project at the Euopean Geophysical Society (EGS) 2002.

TeamSat is the first ESA spacecraft to be flown with ESA/CCSDS compliant TM and TC systems and the first spacecraft anywhere to exploit the adaptive, asynchronous TM capabilities they support. The paper presents the data handling system of the TeamSat dual spacecraft. Authors: Calum Smith, Peter Sinander, Sandi Habinc (ESA/ESTEC TOS-ESM), et al.

The TeamSat dual spacecraft launched by the Ariane 502 test launch was completed in record time and very low cost. The data handling system was ready to support final integration and testing in 6 months despite the fact it had to be designed from scratch. Authors: Calum Smith, Peter Sinander, Sandi Habinc (ESA/ESTEC TOS-ESM), et al.

Large part of the glue logic for the TeamSat TM/TC system was implemented in two Field Programmable Gate Arrays (FPGAs). This document specifies all functional requirements. It is assumed that the reader has previous knowledge about ESA/CCSDS packet TM/TC standards and components implementing them. Author: Sandi Habinc (ESA/ESTEC TOS-ESM).

Component and process qualification, detail component specification of developed ASICs and standard components and other issues related to the procurement are handled through the ESA/SCC System for Electronic, Electrical and Electromechanical Components.

An overview of the ESA Procedures, Specifications and Standards (PSS) documents concerning Space Data Communications.

The Consultative Committee for Space Data Systems (CCSDS) is an international organisation of space agencies interested in mutually developing standard data handling techniques to support space research, including space science and applications, conducted exclusively for peaceful purposes.