The RISC-V in Space Workshop is organized by the ESA Microelectronics Section. The objective is to stimulate the exchange between different parties in Europe, providing or developing space specific microprocessors, IP cores or software solutions based on the RISC-V Instruction Set Architecture.
Schedule, abstracts and presentations
08:30 Coffee / Welcome
Roland Weigand, Felix Siegle ESA
After first - small - steps in previous years, we are glad to see that RISC-V is now heading to space in fast forward mode. IP cores from multiple sources are available on the market, ranging from tiny microcontrollers up to high performance cores with parallel processing datapath. While research studies, IP extensions, benchmarking continue and are being extended, several sensible chip development contracts in advanced technologies have been released lately by ESA (GR7xV, GR765) and NASA (HPSC), accompanied by efforts related to the SW ecosystem, operating systems, hypervisors and AI inference. We furthermore note the first flight use case in a cubesat, but also the interest by a major European space prime. For the future, beyond standard microprocessors and IP cores, we would like to introduce RISC-V also as a hard-macro into space FPGAs.
The presentation will also introduce the COYOTE, a tiny RISC-V core developed as a personal hands-on project by ESA colleague Felix Siegle.
The progress confirms the attractiveness of RISC-V as a successor of the very successful SPARC in space, both being open Instruction Set Architectures.
Mike Eftimakis Codasip
Processor customisation is the best way to significantly improve compute efficiency, without changing of process node. Additionally, it would be extremely interesting to be able to customise the processor after it has been manufactured, so that it is perfectly tuned to each of the applications where the same chip is used.
The combination of Codasip tools and Menta eFPGA technology enables this feat: designers can use the tools and IP from these two European companies to create ultra-efficient, re-configurable processors. Using a combined toolchain enable hardware designers to create their chips and software designers to profile code, estimate performance and benefit from a development environment, automatically customised for each application.
Gerard Rauwerda, Ian Baak Technolution B.V.
"As a founding member of the RISC-V Foundation, Technolution has designed and implemented the FreNox RISC-V processor family. The FreNox RISC-V technology has been integrated in a wide variety of qualified security products for line encryption and domain separation at multiple confidentiality levels. We have ported the full AXI-4-based FreNox RISC-V system-on-chip into the NanoXplore NG-Medium device, and have created a full interactive demonstration; through the SpW-interface we upload software in the RISC-V SoC, allowing the user to play the ""Space Invaders"" game on the NG-Medium board.
We keep improving our RISC-V platform; for instance with processor-agnostic simple gdb remote interface, implemented and demonstrated in the FreNox RISC-V processor. We have designed and implemented a simple gdb remote interface for multiple platforms to make gdb over a serial link a practical proposition for embedded microcontroller use. The implementation comes with limited hardware overhead."
Andy Frame SiFive
The next-generation High Performance Spaceflight Compute (HPSC) will utilize multiple RISC-V Vector cores to deliver 100x the computational capability of today’s space computers. This massive increase in computing performance will help usher in new possibilities for the widest variety of mission elements such as autonomous rovers, vision processing, space flight, guidance systems, and communications. This talk will describe some of the key unique technology benefits that the SiFive Intelligence X280 RISC-V Vector processor brings to the future of computing among the stars.
10:40 Coffee Break
Michael Rogenmoser (+), Yvan Tortorella (x) ETH Zürich (+) / University of Bologna (x)
Since 2013, the Parallel Ultra-Low Power (PULP) platform has released RISC-V cores, interconnects, accelerators, peripherals and full systems-on-chip (SoCs), ranging from simple, single-core microcontrollers to multi-core, heterogeneous systems. The newest SoCs feature RV64 application processors with vector units (RVV) supporting Linux and OpenMP-based offloading of compute-intensive tasks to custom dedicated accelerators and tightly integrated RV32 multi-core clusters. All these designs have been open-sourced under a liberal (Apache-style) license, allowing for easy integration and re-use, even in commercial products.
In the last couple of years we have been working to extend PULP for highly-reliable and high-performance computing, leveraging our heterogeneous and scalable multi-core configurations. In this talk, we present: (i) an overview of the open-source PULP ecosystem and (ii) recent results and ongoing work aimed at extending our multi-core compute cluster with design-time and run-time configurations for reliable operation in space applications.
Jan Andersson Cobham Gaisler AB
Gaisler is a leading vendor of processor ASSPs and IP cores for space applications. The company has developed the NOEL-V RISC-V processor model that can be configured at implementation time in a range of configurations between RV32IMA and RV64GCH. The NOEL-V core is currently being applied both in FPGA and ASIC designs and has recently achieved flight heritage.
The presentation will provide a status update of the space-grade SoC ASSP developments GR765 and GR7xV that are performed within ESA activities. Within these activities, several extensions are being made to the NOEL-V processor core and supporting peripherals to create SoC systems that will have software support during the long product lifetimes associated with the space industry.
The focus of the presentation will be the NOEL-V IP core and corresponding ecosystem, providing a comparison of the state of RISC-V vs SPARC32 (LEON) software ecosystems.
Luca Cattaneo Microchip
An overview of Microchip's RISC-V FPGA & SoC based Solutions, supporting a variety of Instruction Set Extensions, bus connectivity & on-board memory options to allow design engineers to create custom platforms.
The capability to meet specific mission requirements with the lowest power consumption, highest level of performances in the smallest form factor.
The System on chip Multicore platform with its innovative architecture offers a deterministic & coherent RISC-V CPU cluster enabling support for both OS (Linux, RTEMS) and real-time applications.
Carles Hernández UPV (Univ Politecnica de Valencia)
The SELENE RISC-V platform is an open-source RISC-V heterogeneous multicore system-on-chip (SoC) that includes 6 NOEL-V RISC-V cores and artificial intelligence accelerators. In this talk, we will describe the main features of the SELENE platform like the built-in support for safety, the hypervisor-based software architecture, and the full-stack artificial intelligence acceleration support. Finally, we will show performance results of two space-related use-case applications that have been ported to this platform.
12:50 Lunch break
Jimmy Le Rhun Thales R&T (TRT)
The De-RISC project (Dependable Real-time Infrastructure for Safety-critical Computer) provides the first complete processing platform for aeronautics and space, leveraging RISC-V cores, state-of-the-art hypervisor technology and advanced monitoring techniques. It combines a multi-core System-on-chip based on NOEL-V cores from CAES Gaisler, the XNG hypervisor from fentISS, the SafeSU monitoring module from BSC and validation use-cases from Thales Research & Technology. Running from 2019 to 2022, this EU-funded H2020 project has accomplished the productization of the complete platform, fully developed in Europe. The achieved results include, among others: support for full virtualization, support for LithOS and RTEMS guest OS, the development of a cPCI Serial Space board, radiation testing and porting the application framework for payload (LVCUGEN) from CNES.
Dejan Gačnik Skylabs
NANOsky satellite platform has been featured with new OBC product based on new RISC-V processor architecture. The performance enrichments are not gained by jeopardising any fault tolerance on the SoC. That is assured by integrating NOEL-V FT architecture and overall fault tolerant design of SOC and OBC as such. The RISC-V based OBC has been launched to MEO orbit as part of TRISAT-R mission, in order to demonstrate robustness of the equipment and validate fault tolerant features.
Martin Daněk daiteq s.r.o.
The presentation will discuss arithmetic performance of multi-core configurations of the NOEL-V RISC-V processor IP core provided by Cobham Gaisler. The discussion will be mostly focusing on CoreMark-Pro and FPMark benchmarking results that sample the NOEL-V integer and floating-point performance, the latter for three different FPUs that are currently available for NOEL-V - nanofpunv, daiFPUrv and GRFPUnv. The multi-core NOEL-V performance will be put in context with a 4-core U54 RISC-V configuration used in the PolarFire SoC devices provided by Microchip. The performance of the standard NOEL-V instruction set will be complemented by a presentation of advantages of custom arithmetic instructions and low-level floating-point and integer data formats for NOEL-V, developed by daiteq, that are suitable e.g. for implementation of complex floating-point arithmetic, or more-efficient digital signal processing with low-precision integers.
Michael Ryan O.C.E. Technology Ltd.
OCEOSmp is designed for high reliability systems. It facilitates policing system behaviour so that problems can be detected before they result in faults, and allows harts be taken out of use and a task disabled or current execution killed if required. The same code can be run on multiple harts to check all are working correctly, or with different data pointers to speed up a calculation by doing different parts in parallel. Harts can be taken out of active use, restored to use, reserved for use only by high priority tasks, and harts can also be reserved for use by other applications including by other RTOS. The design requires only one system stack per CPU rather than one per task and simplifies schedulability analysis with unbounded priority inversion and chained blocking excluded by the design. Tasks have fixed priorities and pre-emption thresholds with pre-emptive scheduling distributing them symmetrically across the active harts. Up to 255 harts can be used, and mutexes, read/write mutexes, counting semaphores and data queues are provided, and in addition actions can be set to occur at precise times independent of scheduling.
15:30 Coffee Break
Dario Pascucci Thales Alenia Space Italy
In space domain, as well as in other industrial sectors, there is a growing need to support applications with high performance capabilities, especially in terms of computation and reliability. Edge computing is an essential element for the development of onboard applications in new generation space systems, such as HKTM data exploitation for spacecraft prognostics and early detection of anomalies (enhanced-FDIR), onboard SAR data exploitation for enhanced EO constellations, etc. This new paradigm requires the availability of advanced computing platforms and accelerators. RISC-V cores and accelerators represent an open source enabling technology for implementing ML-models, allowing scalability, long lead impact for future support w.r.t. the current state-of-the-art solutions. In this talk, we present: (i) a sample of use cases in space domain which are expected to benefit from edge computing and (ii) a preliminary RISC-V architecture for onboard data processing as resulting from ongoing studies and joint-projects with University/Research team.
Dr Pablo Ghiglino Klepsydra Technologies
Klepsydra software is able to execute Artificial Intelligence (AI) on onboard computers with limited computational capability. Klepsydra AI enables these computers consume up to 50% less energy and process up to 4 times more data than market leaders. The current commercial version of Klepsydra AI has been successfully validated in an ESA activity called KATESU, aimed at running Klepsydra AI on a Space qualified computer, with outstanding performance results.
After the success of this project, Klepsydra has submitted a proposal to the Swiss Space Office for the adoption of Klepsydra AI to the GR765/NOEL-V processor running on RTMES5 operating system.
This project is intended to be a GSTP element 2 and with a duration of 12 months. The goal of this development is to bring the developed technology from TRL4 to TRL7 and to carry out a performance validation on space qualified hardware.
Since Klepsydra AI currently only support Linux operating system and ARM and x86 processor family, the adoption effort will involve substantial changes to the software. Therefore, an in-depth study was carried out to produce a detailed design and implementation plan. This presentation describes in technical terms the planned project, timeline, and roadmap.
Dr Leonidas Kosmidis Barcelona Supercomputing Center (BSC)
European hardware non-dependence is a strategic goal for European Union and ESA member states. Barcelona Supercomputing Center is heavily involved in the RISC-V movement with a wide range of contributions varying from hardware design for FPGA and ASICs, to compilers, programming models and application software. While several of these developments are focused on the high performance domain as part of the European Processor Initiative (EPI) and eProcessor projects, several developments target specifically the space domain as well as other safety critical industries such as the automotive sector. In this talk we provide an overview of the open source RISC-V processor IP developments and software support which aim at increasing the performance capabilities of existing space processors through architectural designs such as vector processing and accelerators, as well as to guarantee or verify their safe execution. Moreover, we will briefly present the current status of the open source BSC Lagarto processor design and the series of its tape outs. We will conclude the presentation with the roadmap of the BSC RISC-V developments and an outlook of the applicability of its high performance designs to safety critical domains in the future.
Sebastian Huber embedded brains GmbH & Co. KG
The history and status of the RISC-V support of the real-time operating system RTEMS is presented. The RISC-V architecture support of RTEMS is compared to other RISC architectures such as ARM, PowerPC, and SPARC. Some potential shortcomings in the PLIC/CLINT interrupt handling are discussed.
17:40 END
Last edited Thu Dec 15 13:52:12 2022