Moving along the adaptation of industrial standardised components for space, ATMEL Wireless and Microcontrollers and ESA have continued their effort to deliver the power required by modern application. Backed by several years of intensive use, the ERC32 computer have moved from a 3- chip version to a monolithic piece of silicon with dramatic improvement in speed, resistance to radiation and power consumption. Saving 70% of space and weight, it allows denser equipment at lower price. Moreover, it hosts an On Chip Debugger (OCD) for non-intrusive program execution control during software development and validation.

The EVI32 device is a VME circuit designed to interface the following components from ATMEL: TSC695E Single Chip Sparc Processor or TSC691E/TSC692E/TSC693E Triple Chip Sparc Processor or TSC21020E DSP associated with the DPC ASIC Companion Chip. The EVI32 device fully adheres to the IEEE 1014-1987 VMEbus. EVI32 can act as a system controller and provides both master and slave interfaces. EVI32 implements the following functions: A32/A24/D32/D16/D8 master interface, A24/D32/D16/D8 slave interface, interrupt handler, interrupter, single level arbiter (SGL), VME bus timer, optimised D16 interface, four mailboxes for multi-processor communication. EVI32 is manufactured by using the MG2RTP gate array family of ATMEL associated with SEU hardened D flip-flop in order to get a very good tolerance to space radiation environment. EVI32 will be available as an ASSP from ATMEL (France).

The level of integration of radiation tolerant technology is continuously increasing. By now, 0.35 um CMOS technology are available for space applications, an adaptation of 0.25 um or 0.18 um processes are in progress. More than 1 million gate ASIC can be designed and soon this figure will be increased to 2 or 3 million gates. Such level of integration allows to envisage the integration of complex systems on the same die. Astrium Vélizy is currently performing a contract managed by ESA in order to study the integration of such complex system within an ASIC. A review of candidates applications have been performed and it has been decided to integrate the core digital functions of a data handling and control system named Spacecraft Controller-on-a-Chip (SCoC). The requirements and the architecture of the SCoC have been defined in this Call Off Order and will be briefly presented.

To answer to applications which require high performance computing with very strong real time constraint Astrium has developed a Multi Chip Module (MCM) solution based on the TSC21020F DSP and the DSP peripheral controller ASIC (DPC) developed in the frame of an ESA contract. This product which fits with a large range of applications has already been used in many space units in particular for Rosetta and Mars Express Spacecraft. This DPC ASIC is available as a standard product from ATMEL Nantes and the MCM DSP is available of-the-shelf from Astrium. This presentation describes the main features of the DPC ASIC and the MCM DSP, the development approach, the validation and qualification test results as well as the development lessons learned.

The SMCSLite 1355 chip provides an interface between the serial IEEE-1355 link and a highly configurable parallel data bus. Additional features of this device are on-chip facilities like timers, FIFO control, ADC/DAC interfaces, UARTs etc. The device can be completely remotely controlled via the IEEE-1355 link without the need for a local microcontroller, FPGA or similar. The SMCSLite was developed at ASTRIUM GmbH in Munich-Ottobrunn during 1998 with partial funding under a CEC (DIPSAP-II) contract and has been implemented in a MH1RT gate array from ATMEL W&M. The presentation will cover the features of the SMCSLite, its recent validation at ASTRIUM in Ottobrunn and the production of a DS-link macrocell as a stand-alone element. The test board used to validate the SMCSLite functionality will be described.

The second-generation Advanced GPS/GLONASS ASIC, the AGGA-2, supports a variety of GPS/GLONASS receivers and instruments for space applications, including high precision scientific applications such as atmospheric sounding by radio occultation, Spacecraft Control with navigation and attitude determination, reference stations, etc. The AGGA-2 has 12 single-frequency channels, each capable of tracking a GNSS C/A-code signal on any carrier frequency. Two single- frequency channels can be configured for attitude determination according to the Hybrid Parallel-Multiplex Architecture (RD5). Three single-frequency channels together with a P-code Unit can be configured into one dual- frequency channel capable of tracking a GNSS C/A-code signal on one carrier frequency (e.g. L1) and a GNSS P-code or Y-code on two carrier frequencies (e.g. L1 and L2).

ATMEL, in partnership with Alcatel Space, has developed Viterbi and Reed Solomon decoders for DVB-S type of applications. The presentation will explain how this has been achieved through the VHDL models validation using noisy transmission system simulation files, the design of a complete DVB-S chain decoding chip which allows to isolate each individual blocks by in chip programming, and the validation into an actual application by Alcatel Space. In addition, ATMEL has set a special encoding scheme which allows the chip to keep operating, even in a burst mode operation. The supporting ASIC library will be documented and the actual results and performances will be reported. Finally, a status will be done as to the current availability of such functions.

A Fault Tolerant Computer for Space Applications Architecture, Reconfiguration Strategy and I/O Controller. In the framework of an ESA contract, the architecture and technology for On Board Fault Tolerant Computers have been studied by Saab Ericsson Space, Sweden. The study has focused on three main topics; the overall architecture, the Reconfiguration Strategy and the I/O Controller. A number of candidate architectures for the processor core were defined and a trade off between them was performed. A Spacecraft Management Unit (SMU) based on the selected architecture was defined in more detail. Within the SMU two key building blocks were developed, the Reconfiguration Electronics and the CPU Companion I/O Controller (COCOS). The Reconfiguration Electronics is based on a dual redundancy concept. It is highly configurable allowing its use in any type of mission without unnecessary complexity overhead. The I/O controller is developed primarily as a support device to the ERC32SC and LEON CPUs. It acts as a bridge between the CPU and a number of I/O channels. It also provides bulk memory control and a PCI interface.

The Next Generation Technology TM/TC System (NTTS) represents the latest development of the Satellite Services B.V. TM/TC processing product range and forms part of the SpaceLinkNGT family. This uses the latest System-on-a-programmable chip techniques to provide a highly integrated, high performance and yet flexible TM/TC system. This system builds on successful experiences with spacecraft such as XMM, INTEGRAL, MSG, ROSETTA, Mars Express etc and is aimed at providing a complete TM/TC system for spacecraft AIT, system level development, integration and testing as well as SatCom terminals. The system can also be scaled and customised to meet an individual customers needs. The system includes, TM reception and decomutation (Viterbi Error Correction, Frame Synchronisation, Reed-Solomon error detection and correction, De- Randomisation, frame analysis, packet extraction etc.), TM Simulation from packets down to encoded bit streams (including Reed-Solomon encoding etc), TC generation and encoding (CCSDS Packet TC standard supported), TC reception and packet extraction. The system provides a large amount of visibility into the received and transmitted data as well as diagnostic information and logging. The system may be used both locally through the local GUI or remotely supporting an open software architecture where LAN protocols can be used but also allowing third party software to be easily integrated through the system API.

Integrated circuits offer certain advantages in respect to discrete implementations: lower weight, lower power consumption, high reliability, etc. Especially with the advent of radiation tolerant, digitally compatible CMOS technologies the use of integrated circuits for space application (sensory interfaces, environmental monitoring, etc.) has received a lot of attention. In integrated circuit design the digital design field is supported by a large number of commercially available design tools offering both automation and verification. This is important since integrated circuits have a rather long design cycle and design errors are thus extremely costly. In analog design less tools are available. However the same problem exists: redesigns are costly and time-consuming. Therefore part of the project effort has been directed towards the design and implementation of analog design tools reducing the cost of analog design. The AMGIE toolset, that has been developed in a preceeding ASTP4 project, has been extended and complemented by a number of point tools targeting the applications of this project. The AMGIE toolset has been extended to allow synthesis of more complex analog circuits as for instance Charge Sensitive Amplifiers - Pulse Shaping Amplifier (CSA-PSA) circuits. The LAYLA layout tools (part of AMGIE) now include special layout structures that are capable of handling larger radiation doses: Gate all around or edgeless devices. The Mondriaan tool targets the generation of high speed A/D-converters (part of this project) and D/A-converters. Mondriaan generates high quality regular layout structures in a short time that are DRC correct. Included are a number of bus and tree generators that speed up the assembly of the different modules. Symbolic analysis has been applied to regenerative comparators, which are an essential building block of high speed A/D-converters. A comparator verification tool built upon MIMI extracts the offset by inserting appropriate mismatch models. This work has been reported in a number of publications on international conferences and has increased the design productivity in this project through early adoption by the designers.

High-speed data converters still require large design times because of their complexity and the lack of dedicated analog design tools. Although design automation tools are capable of generating moderate complex analog building blocks (e.g. operational amplifiers), the design of highly complex or state-of-the-art analog blocks components is still done manually. To speed up the design considerably dedicated point tools have been developed within this project. As test engine a high-speed 100 MS/s A/D converter for base stations applications has been developed. The use of behavioral models allows the designer to simulate INL and DNL within minutes (compared to several hours for transistor level simulations like hspice). The design equations needed for this model were automatically derived using symbolic analysis tools. For speeding up the layout phase of the design, a novel point tool called Mondriaan has been developed. This tool is targeted for layout generation of very regular layout structures (such as D/A converters and A/D converters). Using this set of point tools a high- speed 100MS/s full CMOS A/D converter core has been successfully designed, a layout has been generated and the chip has been processed and characterized in the 0.35u Alcatel-CMOS technology. The chip is functionally working as expected. Because of an error in the interface layer between the analog pre-processing stage in the A/D converter and the digital back-end decoder however, this first design was not within spec. This error has been corrected in a redesign.

PDFE (Particle Detector Front-End) is a low power low noise mixed analogue- digital custom chip developed by IMEC for ESA and intended for scientific energetic particle space born instrumentation (spectroscopy). The ASIC (application specific integrated circuit) is designed in a standard 0.7-um CMOS process. The chip comprises a charge sensitive amplifier, a semi-gaussian pulse- shaping amplifier, a peak detector, a discriminator with a programmable threshold, an 8- bit ADC and control logic. A second channel is provided for (anti-)coincidence purposes. For cost reasons the circuit is made as versatile as possible by providing several, digitally programmable, configurations. ENC (Equivalent Noise Charge) is 1000e¯rms (measured) at 100pF detector capacitance, 1nA detector leakage and a shaper peaking time of 1us. Conversion gain is 30mV/fC and full scale input is 0.1 pC. Power consumption is 70mW when all blocks are enabled. Power supply is 5 V. The die area measures 31mm². A baseline shift of 15mV is realised at 250Ksamples/s (this is the maximum counting rate) for inputs limited to 2.5 fC and at 25 ksamples/s for full scale inputs. Radiation hardness is implemented both at the transistor level (analogue cells) and at the architectural level (digital part).

Demonstrators like Visual Telemetry System on TeamSat, and Visual Monitoring Camera on XMM-Newton and Cluster II indicate the usefulness of compact visual inspection cameras on spacecraft. IRIS is a CMOS camera-on-a- chip developed for this purpose. It contains a 640x480 pixel resolution at 10 frames per second, 8 bit ADC, on-chip timing and control for sub sampling and windowing, CCSDS packet telecommand and telemetry handling, and various input and output interfaces. The chip was implemented in ALCATEL Microelectronics' standard 0.7um CMOS process, and afterwards it was electro-optically characterised and irradiated. Small demonstration cameras have been built, comprising of the IRIS2 chip, line drivers and receivers, power supply, and clock generator.

The use of autocorrelation spectrometers is planned for several future space missions with applications in radiometers for both aeronomy and astronomy. The core of such an instrument consist of a correlation DSP and an ADC, both realised as ASIC's in most modern applications. State of the art in 1997 was the spectrometer in the ODIN project, with both full custom correlation DSP and an ADC, where especially the power consumption was much lower than previously achieved, about a factor 10- 20 lower. Based on several future applications, including instruments on FIRST, Soprano and Master, but also on design techniques to achieve very high clock rates combined with low power consumption, an ESA technical development project was started. The target for this project was to lower power consumption with a factor of 5 while rasing effective clock rate with a factor of 5. This was achieved and both the overall design will presented as well as some design details. In addition to the technical details, some applications with also be shown, including HIFI for FIRST, SMOG for SMART-1 and Marshal (Master demonstrator). This project is now continued with a new generation chip set, aiming at reducing power and raising clock rates consumption, but also at increasing packaging density to the level of single chip spectrometers. Some results from this will also be presented.

In the framework of this contract the effects of radiation on CMOS active pixels were studied and a design methodology was developed to improve significantly their radiation tolerance (> 200 kGy(Si) from a Co-60 source). The total dose tests on the standard nMOS pixels revealed problems related to the transistors, photo diode and interconnectivity due to parasitic field transistors and junction leakage currents. By appropriate layout of the pixel the rapid dark current increase in standard pixels can be avoided while leaving the opportunity for high collection efficiency, fill factor, sensitivity and low cross-talk, and the best trade-off between them for a given application. Moreover, because the obtained radiation tolerance does not result from any modification in the standard process technology, the applicability of the radiation tolerant design techniques is not limited to a certain CMOS technology.

This project aims at the development of an image sensor for a beam-tracking device that can withstand the high radiation load in low orbit. An instrument containing a CMOS image sensor can offer several benefits in terms of cost-effectiveness, weight and volume. The design of this image sensor started from the experience that was gained during the design and the realisation of the Across sensor for star-tracking applications. A number of specifications of this array also apply for the new design: pixel size, array format, and noise performance. However, a number of enhancements were necessary to turn it into a flight-worthy component for beam-tracking applications. These requirements are:, enhanced radiation tolerance, enhanced ADC resolution, improved MTF, improved infra-red response, addressable windowing. Starting from these requirements a new sensor was designed employing the new radiation- tolerant design technique that were recently developed at IMEC and FillFactory. This presentation reports on the design and the production and the evaluation of this sensor and gives an overview of its main specifications.

A new ECSS Standard for ASIC Development is under preparation and a draft document is available for review by industry. The new document will replace the ESA Design and Assurance Requirements - QC/172/RdM and the ASIC Design and Manufacturing Requirements - WDN/PS/700.