The Use Of Reprogrammable FPGA In Space

Flipper Product Sheet (Format: Adobe PDF) 

Flipper Executive Summary (Jan 2009) (Format: Adobe PDF) 

The FLIPPER test system has been developed by IASF Milano under ESA contract. FLIPPER allows injection of SEU-like faults into user flip-flops, configuration memory and reconfiguration control registers of a Xilinx FPGA. This allows testing the impact of configuration SEU on unprotected designs, as well as evaluating the efficiency of fault mitigation methods.

Suitability of reprogrammable FPGAs in space applications (Format: Adobe PDF) 

"Field Programmable Gate Array (FPGA) devices have been used in space for more than a decade with a mixed level of success. Until now, few reprogrammable devices have been used on European spacecraft due to their sensitivity to involuntary reconfiguration due to Single Event Upsets (SEU) induced by radiation. But with the advent of reprogrammable devices featuring a million systemgates or more, it is not longer feasible to disregard these technologies."
This document concentrates on SRAM based FPGA devices from Xilinx. Through a comprehensive bibliography, it illustrates SEU failure mechanisms and susceptibility, SEU mitigation approaches and summarises (radiation) test results. Author: Sandi Habinc.

Functional Triple Modular Redundancy (FTMR) (Format: Adobe PDF) 

"VHDL Design Methodology for Redundancy in Combinatorial and Sequential Logic"
Further expands the 'logic replication and voting in combinatorial and sequential logic', mentioned in the previous document. In particular implementing redundancy in combinatorial logic is a challenge, since commercial synthesis tools aim to remove any logic redundancy. A VHDL coding method is developed, which reliably allows to infer configurable levels of redundancy in registers and combinatorial logic. Code examples are given as well as synthesis and layout results. Author: Sandi Habinc.