Advanced ASIC and FPGA technologies allow to integrate complex systems on a single chip, embedding standard processor devices, dedicated processing blocks, interfaces to various peripherals, on-chip bus structures in a SOC, or even analog blocks in a mixed-signal device. Moving away from the use of traditional components towards SOC technology will help to satisfy the ever-increasing demands for high processing performance, while reducing mass and power consumption.
With increasing complexity, the design methodology has changed from being gate-level oriented to the integration of complex building blocks (IP-cores). Tasks, which traditionally are considered as 'system-design', such as interface specification, bus throughput assessment etc. are now part of the chip design. The designers have to rely on pre-existing building blocks, ideally with already verified functionality, documentation and production test vectors being available. But different IP-blocks from various origins imply different coding styles, documentation and verification levels. Their interoperability and compliance to the overall SOC specification ultimately has to be verified on chip level.
Besides the technical issues, core-based design is also a challenge on the legal side, when it comes to the integration of IP blocks from various origins, bound to different licensing conditions, prices and non-disclosure agreements.
The European Space Agency promotes the use of SOC in space by the means of SOC development activities, IP-core development/distribution and documentation relating to on-chip bus systems and design methodology. These activities are presented in the following sections.
Synthesisable IP-Cores, mostly in VHDL language, developed by ESA or under ESA contract, which can be licensed under certain conditions.LEON2(-FT) Sparc V8 Development
The LEON2 core is a SPARC V8 compatible processor developed for future space missions. LEON2 is based on the AMBA AHB and APB on-chip buses. It has been implemented as a highly configurable, synthesizable VHDL model, which exists in two versions:
- A Single-Event-Upset (SEU) fault-tolerant version, called LEON2-FT, involving complete TMR protection for all flip-flops and EDAC protection for all memories is the base of the AT697 microprocessor, on radiation hard 0.18 um technology. A test-chip (LEONUMC) has been implemented by the Microelectronics Section in commercial 0.18 um technology from UMC.
- A non fault-tolerant version is freely available under the GNU Lesser General Public License. For further information, please refer to Leon2 page at www.gaisler.com and download source code from the Leon2-XST repository.
|Title||Description and additional links||Prime contractor||Dates|
|Chipsat||A System-on-a-Chip for Small Satellite Data Processing and Control. SOC requirements for small satellites were specified, and a ChipSat design built around the LEON processor core was implemented and tested on FPGA. A software implementation of a CCSDS Telecommand/Telemetry (TM/TC) loop was developed and tested with this platform.||Surrey Space Centre, Guildford, UK||Closed Q1/2003|
|SCOC1||The Spacecraft Controller On a Chip (SCOC) architecture, using the LEON processor, provides hardware TM/TC functionality, dual on-chip bus architecture to ensure high data throughput and various interface modules. The objective of this contract, called "Building Blocks for System On-a Chip", was to conduct an architectural feasibility study, to specifiy and to implement a first SCOC architecture based on the LEON1 processor core. This architecture was prototyped in an FPGA on the BLADE (Board for Leon and Avionics DEmonstration). Another objective was to gain experience with the integration of IP-cores of various origins into a single design. Other documents/presentations||Astrium SAS, Velizy (F)||Closed Q2/2004|
|SCOC3||Followup to the SCOC1 contract, with the objective to finalise the architectural design for a SCOC-ASIC and to conduct a feasibility study on target ASIC technology. This implies updating the architecture (using LEON3 and new versions of other IPs), development of additional building blocks, verification by simulation and FPGA prototyping and synthesis to target technology.||Astrium SAS, Velizy (F)||Started Q3/2006|
|AGGA3||AGGA3 is the next generation GNSS baseband ASIC, successor of the AGGA2, targeting in particular earth observation applications. Besides a GNSS block with front-end and multi-channel correlators, it integrates the LEON2 processor and several Spacewire interfaces. It is also an example for a SOC reusing IP's from diverse origin.||Astrium GmbH, Ottobrunn (D)||Started Q1/2003|
|COLE||The COLE ASIC will merge the Leon2 SPARC processor with all bus interface support needed to implement spacecraft processing and control and to control mass memories or payloads.||Saab Ericsson Space, Gothenburg (S)||Manufacturing Q3/2007|
|RTC||The SpaceWire Remote Terminal Controller ASIC is to be used for controlling scientific instruments and to process their data. The Leon2-FT SPARC processor constitutes the core of this circuit, to serve as a link between a satellite high-speed SpaceWire backbone network and local, low-speed CAN buses serving individual instruments (ESA press release).||Saab Ericsson Space, Gothenburg (S)||Manufacturing Q3/2007|
File is under the GNU Lesser General Public License.Example of an AMBA system
File is under the GNU Lesser General Public License.
High integration levels of microelectronics will be required to fulfil increasing performance demands. Implementations will move from traditional components towards more advanced single-chip systems. The design methodology will be to integrate complex building blocks Author: Sandi Habinc (ESA/ESTEC TOS-ESM).Designing Space Applications Using Synthesisable Cores
This paper concentrates on how building blocks for microelectronics are developed in VHDL and how they are purchased, distributed and used in the scope of European Space Agency (ESA) activities, ranging from in-house developments to contractor work and from simple Field Programmable Gate Arrays (FPGAs) to complex System-On-a-Chip (SOC) designs. Author: Sandi Habinc (ESA/ESTEC TOS-ESM).Accelerated Verification of Digital Devices Using VHDL
This paper presents two aspects for improving the verification of microprocessors; program-less verification, and methods for handling large differences in abstraction level between a reference model and the actual design. Program-less verification is a type of pseudo random verification where the notion of a software program executing on the microprocessor has been abandoned. Author: Sandi Habinc and Peter Sinander (ESA/ESTEC TOS-ESM).
Information available from ESA concerning High-Reliability ASIC and FPGA design for space applications.VHDL Modelling Issues
Public information related to VHDL.
Last edited 17 April 2007