--============================================================================--
-- Design unit  : AMBA Example (Entity and architecture declarations)
--
-- File name    : amba_example.vhd
--
-- Purpose      : The declaration of various AMBA modules in this files are used
--                for illuminating the usage of the AMBA VHDL package.
--
-- Reference    : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
--                13th May 1999, issue A, first release, ARM Limited
--
--                The document can be retrieved from http://www.arm.com
--
--                AMBA is a trademark of ARM Limited.
--                ARM is a registered trademark of ARM Limited.
--
-- Note         : Naming convention according to AMBA(TM) Specification:
--                   Signal names are in upper case, except for the following:
--                      A lower case 'n' in the name indicates that the signal
--                      is active low.
--                   Constant names are in upper case.
--
--                The least significant bit of an array is located to the right,
--                carrying the index number zero.
--
-- Library      : AMBA_Lib {recommended}
--
-- Author       : European Space Agency
--                P.O. Box 299
--                NL-2200 AG Noordwijk ZH
--                The Netherlands
--
-- Contact      : mailto:microelectronics@estec.esa.int
--                http://www.estec.esa.int/microelectronics
--
-- Copyright (C): European Space Agency (ESA) 2000. 
--                This source code is free software; you can redistribute it 
--                and/or modify it under the terms of the GNU Lesser General 
--                Public License as published by the Free Software Foundation; 
--                either version 2 of the License, or (at your option) any 
--                later version. For full details of the license see file
--                http://www.estec.esa.int/microelectronics/core/copying.lgpl 
--
--                It is recommended that any use of this VHDL source code is
--                reported to the European Space Agency. It is also recommended 
--                that any use of the VHDL source code properly acknowledges the 
--                European Space Agency as originator. 
--
-- Disclaimer   : All information is provided "as is", there is no warranty that
--                the information is correct or suitable for any purpose,
--                neither implicit nor explicit. This information does not
--                necessarily reflect the policy of the European Space Agency.
--------------------------------------------------------------------------------
-- Version  Author   Date           Changes
--
-- 0.2      ESA       5 Jul 2000    Example file created
-- 0.3      ESA      10 Jul 2000    Additional HREADY slave input,
--                                  Std_ULogic usage for non-array signals,
--                                  Additional constant usage in examples,
--                                  Changed AHBArbiter to AHBArbiterDecoder
-- 0.4      ESA      14 Jul 2000    AHBArbiterDecoder architecture added
--                                  HRESETn removed from AHB Slave input record
-- 0.5      ESA      30 Aug 2000    Vector types for AHB arbiter/decoder and
--                                    APB bridge refined, and corresponding
--                                    record types removed
--                                  Name suffix 'x' removed
--          ESA      04 Feb 2002    Changed copyright text
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------
-- Examples of AMBA AHB Master, Slave and Arbiter/Decoder entity declarations
--------------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;

library Work;
use Work.AMBA.all;

entity AHBMaster is
   port(
      HCLK:          in    Std_ULogic;
      HRESETn:       in    Std_ULogic;
      AHBMasterIn:   in    AHB_Mst_In_Type;
      AHBMasterOut:  out   AHB_Mst_Out_Type);
end AHBMaster;

architecture RTL of AHBMaster is
begin
    AHBMasterOut  <= (HBUSREQ   => '0',
                      HLOCK     => '0',
                      HTRANS    => HTRANS_IDLE,
                      HADDR     => (others => '0'),
                      HWRITE    => '0',
                      HSIZE     => HSIZE_BYTE,
                      HBURST    => HBURST_SINGLE,
                      HPROT     => (others => '0'),
                      HWDATA    => (others => '0'));
end RTL; --===================================================================--

library IEEE;
use IEEE.Std_Logic_1164.all;

library Work;
use Work.AMBA.all;

entity AHBSlave is
   port(
      HCLK:          in    Std_ULogic;
      HRESETn:       in    Std_ULogic;
      AHBSlaveIn:    in    AHB_Slv_In_Type;
      AHBSlaveOut:   out   AHB_Slv_Out_Type);
end AHBSlave;

architecture RTL of AHBSlave is
begin
   AHBSlaveOut <= (HREADY     => '1',
                   HRESP      => HRESP_OKAY,
                   HRDATA     => (others => '1'),
                   HSPLIT     => (others => '1'));
end RTL; --===================================================================--

library IEEE;
use IEEE.Std_Logic_1164.all;

library Work;
use Work.AMBA.all;

entity AHBArbiterDecoder is
   generic(
      MASTERS:             Natural := 16;                -- number of masters
      SLAVES:              Natural := 16);               -- number of slaves
   port(
      HCLK:          in    Std_ULogic;
      HRESETn:       in    Std_ULogic;
      AHBMstToArb:   in    AHB_Mst_Out_Vector(0 to MASTERS-1);
      AHBArbToMst:   out   AHB_Mst_In_Vector (0 to MASTERS-1);
      AHBSlvToArb:   in    AHB_Slv_Out_Vector(0 to SLAVES-1);
      AHBArbToSlv:   out   AHB_Slv_In_Vector (0 to SLAVES-1));
end AHBArbiterDecoder;

architecture RTL of AHBArbiterDecoder is
begin
   AHBArbToMst <= (others => (HGRANT      => 'L',
                              HREADY      => 'L',
                              HRESP       => (others => 'L'),
                              HRDATA      => (others => 'L')));

   AHBArbToSlv <= (others => (HSEL        => 'L',
                              HADDR       => (others => 'L'),
                              HWRITE      => 'L',
                              HTRANS      => (others => 'L'),
                              HSIZE       => (others => 'L'),
                              HBURST      => (others => 'L'),
                              HWDATA      => (others => 'L'),
                              HPROT       => (others => 'L'),
                              HREADY      => 'L',
                              HMASTER     => (others => 'L'),
                              HMASTLOCK   => 'L'));
end RTL; --===================================================================--

--------------------------------------------------------------------------------
-- Examples of AMBA APB Slave and Bridge entity declarations
--------------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;

library Work;
use Work.AMBA.all;

entity APBSlave is
   port(
      PCLK:          in    Std_ULogic;
      PRESETn:       in    Std_ULogic;
      APBSlaveIn:    in    APB_Slv_In_Type;
      APBSlaveOut:   out   APB_Slv_Out_Type);
end APBSlave;

architecture RTL of APBSlave is
begin
   APBSlaveOut.PRDATA   <= (others => 'H');
end RTL; --===================================================================--

library IEEE;
use IEEE.Std_Logic_1164.all;

library Work;
use Work.AMBA.all;

entity APBMultiSlave is
   generic(
      SLAVES:              Natural := 8);                -- number of slaves
   port(
      PCLK:          in    Std_ULogic;
      PRESETn:       in    Std_ULogic;
      APBBrgToSlv:   in    APB_Slv_In_Vector (0 to SLAVES-1);
      APBSlvToBrg:   out   APB_Slv_Out_Vector(0 to SLAVES-1));
end APBMultiSlave;

architecture RTL of APBMultiSlave is
begin
   APBSlvToBrg <= (others => (PRDATA => (others => 'H')));
end RTL; --===================================================================--

library IEEE;
use IEEE.Std_Logic_1164.all;

library Work;
use Work.AMBA.all;

entity APBBridge is
   generic(
      SLAVES:              Natural := 16);               -- number of slaves
   port(
      HCLK:          in    Std_ULogic;
      HRESETn:       in    Std_ULogic;
      AHBSlaveIn:    in    AHB_Slv_In_Type;
      AHBSlaveOut:   out   AHB_Slv_Out_Type;

      PCLK:          in    Std_ULogic;
      PRESETn:       in    Std_ULogic;
      APBSlvToBrg:   in    APB_Slv_Out_Vector(0 to SLAVES-1);
      APBBrgToSlv:   out   APB_Slv_In_Vector (0 to SLAVES-1));
end APBBridge;

architecture RTL of APBBridge is
begin
   AHBSlaveOut <= (HREADY     => 'W',
                   HRESP      => HRESP_OKAY,
                   HRDATA     => (others => 'W'),
                   HSPLIT     => (others => 'W'));
   APBBrgToSlv <= (others => (PSEL       => 'W',
                              PENABLE    => 'W',
                              PADDR      => (others => 'W'),
                              PWRITE     => 'W',
                              PWDATA     => (others => 'W')));
end RTL; --===================================================================--

--------------------------------------------------------------------------------
-- Example of complete system with AMBA AHB and APB modules
--------------------------------------------------------------------------------

library IEEE;
use IEEE.Std_Logic_1164.all;

library Work;
use Work.AMBA.all;

entity AMBASystem is
   port(
      HCLK:          in    Std_ULogic;
      HRESETn:       in    Std_ULogic;
      PCLK:          in    Std_ULogic;
      PRESETn:       in    Std_Logic);
end AMBASystem;

architecture RTL of AMBASystem is
   -----------------------------------------------------------------------------
   -- component declarations
   -----------------------------------------------------------------------------
   component AHBMaster
      port(
         HCLK:          in    Std_ULogic;
         HRESETn:       in    Std_ULogic;
         AHBMasterIn:   in    AHB_Mst_In_Type;
         AHBMasterOut:  out   AHB_Mst_Out_Type);
   end component;

   component AHBSlave
      port(
         HCLK:          in    Std_ULogic;
         HRESETn:       in    Std_ULogic;
         AHBSlaveIn:    in    AHB_Slv_In_Type;
         AHBSlaveOut:   out   AHB_Slv_Out_Type);
   end component;

   component AHBArbiterDecoder
      generic(
         MASTERS:             Natural := 16;
         SLAVES:              Natural := 16);
      port(
         HCLK:          in    Std_ULogic;
         HRESETn:       in    Std_ULogic;
         AHBMstToArb:   in    AHB_Mst_Out_Vector(0 to MASTERS-1);
         AHBArbToMst:   out   AHB_Mst_In_Vector (0 to MASTERS-1);
         AHBSlvToArb:   in    AHB_Slv_Out_Vector(0 to SLAVES-1);
         AHBArbToSlv:   out   AHB_Slv_In_Vector (0 to SLAVES-1));
   end component;

   component APBSlave
      port(
         PCLK:          in    Std_ULogic;
         PRESETn:       in    Std_ULogic;
         APBSlaveIn:    in    APB_Slv_In_Type;
         APBSlaveOut:   out   APB_Slv_Out_Type);
   end component;

   component APBMultiSlave
      generic(
         SLAVES:              Natural := 8);
      port(
         PCLK:          in    Std_ULogic;
         PRESETn:       in    Std_ULogic;
         APBBrgToSlv:   in    APB_Slv_In_Vector (0 to SLAVES-1);
         APBSlvToBrg:   out   APB_Slv_Out_Vector(0 to SLAVES-1));
   end component;

   component APBBridge
      generic(
         SLAVES:              Natural := 16);
      port(
         HCLK:          in    Std_ULogic;
         HRESETn:       in    Std_ULogic;
         AHBSlaveIn:    in    AHB_Slv_In_Type;
         AHBSlaveOut:   out   AHB_Slv_Out_Type;

         PCLK:          in    Std_ULogic;
         PRESETn:       in    Std_ULogic;
         APBSlvToBrg:   in    APB_Slv_Out_Vector(0 to SLAVES-1);
         APBBrgToSlv:   out   APB_Slv_In_Vector (0 to SLAVES-1));
      end component;

   -----------------------------------------------------------------------------
   -- constant declarations
   -----------------------------------------------------------------------------
   constant AHBMASTERS:       Natural := 16;             -- number of masters
   constant AHBSLAVES:        Natural := 16;             -- number of slaves

   constant APBSLAVES:        Natural := 32;             -- number of APB slaves

   -----------------------------------------------------------------------------
   -- signal declarations
   -----------------------------------------------------------------------------
   signal   AHBMstToArb:      AHB_Mst_Out_Vector(AHBMASTERS-1  downto 0);
   signal   AHBArbToMst:      AHB_Mst_In_Vector (AHBMASTERS-1  downto 0);
   signal   AHBSlvToArb:      AHB_Slv_Out_Vector(AHBSLAVES-1   downto 0);
   signal   AHBArbToSlv:      AHB_Slv_In_Vector (AHBSLAVES-1   downto 0);

   signal   APBSlvToBrg:      APB_Slv_Out_Vector(APBSLAVES-1   downto 0);
   signal   APBBrgToSlv:      APB_Slv_In_Vector (APBSLAVES-1   downto 0);

begin
   -----------------------------------------------------------------------------
   -- AHB modules
   -----------------------------------------------------------------------------
   AHBArb: AHBArbiterDecoder
      generic map(
         MASTERS           => AHBMASTERS,
         SLAVES            => AHBSLAVES)
      port map(
         HCLK              => HCLK,
         HRESETn           => HRESETn,
         AHBMstToArb       => AHBMstToArb,
         AHBArbToMst       => AHBArbToMst,
         AHBSlvToArb       => AHBSlvToArb,
         AHBArbToSlv       => AHBArbToSlv);

   GenerateAHBMasters: for i in AHBMASTERS-1 downto 0 generate
      AHBMst: AHBMaster
         port map(
            HCLK           => HCLK,
            HRESETn        => HRESETn,
            AHBMasterIn    => AHBArbToMst(i),
            AHBMasterOut   => AHBMstToArb(i));
   end generate GenerateAHBMasters;

   GenerateAHBSlaves: for i in AHBSLAVES-1 downto 1 generate
      AHBSlv: AHBSlave
         port map(
            HCLK           => HCLK,
            HRESETn        => HRESETn,
            AHBSlaveIn     => AHBArbToSlv(i),
            AHBSlaveOut    => AHBSlvToArb(i));
   end generate GenerateAHBSlaves;

   -----------------------------------------------------------------------------
   -- AHB/APB bridge module
   -----------------------------------------------------------------------------
   APBBrg: APBBridge
      generic map(
         SLAVES            => APBSLAVES)
       port map(
         HCLK              => HCLK,
         HRESETn           => HRESETn,
         AHBSlaveIn        => AHBArbToSlv(0),
         AHBSlaveOut       => AHBSlvToArb(0),
         PCLK              => PCLK,
         PRESETn           => PRESETn,
         APBSlvToBrg       => APBSlvToBrg,
         APBBrgToSlv       => APBBrgToSlv);

   -----------------------------------------------------------------------------
   -- APB multi module
   -----------------------------------------------------------------------------
   APBMulSlv: APBMultiSlave
      generic map(
         SLAVES            => 8)
      port map(
         PCLK              => PCLK,
         PRESETn           => PRESETn,
         APBBrgToSlv       => APBBrgToSlv(7 downto 0),
         APBSlvToBrg       => APBSlvToBrg(7 downto 0));

   -----------------------------------------------------------------------------
   -- APB modules
   -----------------------------------------------------------------------------
   GenerateAPBSlaves: for i in APBSLAVES-1 downto 8 generate
      APBSlv: APBSlave
         port map(
            PCLK           => PCLK,
            PRESETn        => PRESETn,
            APBSlaveIn     => APBBrgToSlv(i),
            APBSlaveOut    => APBSlvToBrg(i));
   end generate GenerateAPBSlaves;

end RTL; --===================================================================--