This page provides information on the Next Generation Microprocessor (NGMP) development based on LEON4-FT

After the preliminary GINA study based on LEON3, completed in 2006, Aeroflex Gaisler has started the first development phase of the Next Generation Microprocessor (NGMP) under a TRP contract. This first phase was kicked off in summer 2009, and it comprises the architectural (VHDL) design, verification by simulation and on FPGA. An FPGA demonstrator will be presented by the end of 2010, and the activity should be completed with synthesis on ASIC technology until mid 2011.

The development of Functional Prototypes of the NGMP, called NGFP, has been started in April 2011. These prototypes have been manufactured in 45 nm commercial structured ASIC technology eASIC Nextreme2. While the FPGA prototypes include only a subset of the NGMP features, and their clock frequency is limited to 45 - 70 MHz, the goal of NGFP is to allow functional validation and evaluation by end users of an almost fully fledged NGMP implementation. NGFP contains most of the features of NGMP (except the high speed serial links), and runs at a clock frequency of 150 MHz, which is a good step towards the target of the final space ASIC implementation (300 MHz). Availability of development boards is scheduled for Q1-2013.

Further development phases will cover the manufacturing and validation of prototypes in space ASIC technology and manufacturing and qualification of flight parts. The microprocessor chip development is also complemented by activities in the SW field.

Pictures

NGFP Evaluation Board

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Last edited 24. April 2013