ERC32 VMEbus Interface (EVI32) - specification, synthesizable VHDL model and ASSP component
The EVI32 is a 32-bit VME interface designated to interface the ERC32
processor chip set to the VMEbus. The EVI32 fully adheres to the IEEE 1014-1987
VMEbus standard, and is compatible with the commercial VMEbus specification.
EVI32 can act as a system controller and provides both master and slave interfaces.
EVI32 comprises the following functions:
- A32/A24/D32/D16/D8 master and slave interface;
- Interrupt handler;
- Interrupter;
- Single level arbiter (SGL);
- VME bus timer;
- Optimised D16 interface;
- Four mailboxes for multi-processor communication;
- Minimised usage of external buffers;
The EVI32 specification and VHDL design is a result of an internal ESTEC
development. The design has been implemented in an FPGA and is suitable for
implementation in radiation hard or tolerant ASIC technologies.
The functional specification is available in Adobe PDF format at:
The synthesizable VHDL model with testbenches are available under the
standard ESA licensing conditions.
The VHDL core, adapted to the ERC32 three chip and single chip processors, as well as the 21020 DSP,
has been implemented by Astrium Velizy to the
T7907E chip (datasheet)
under ESA contract 13345. This chip shall be commercialised by Atmel.
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Last edited 26 January 2005
