Area of FW in Xilinx xc2v6000ff1152-4:
--------------------------------------
I/O Register bits:                  12
Register bits not including I/Os:   9141 (13%)

RAM/ROM usage summary
Dual Port Rams (RAM16X1D): 271
Single Port Rams (RAM64X1S): 460
Single Port Rams (RAM128X1S): 1904
Block Rams : 137 of 144 (95%)


Block Multipliers: 31 of 144 (21%)

Global Clock Buffers: 2 of 16 (12%)


Mapping Summary:
Total  LUTs: 35724 (52%)


Max Clock Frequency ~50 MHz (pre-Place&Route)


Implementation of FW in UMC 0.18 with VST libraries:
----------------------------------------------------

***************************************
Report : area
Design : FW
Version: 2003.06-SP1
Date   : Thu Aug  5 15:17:58 2004
****************************************

Library(s) Used:

    umcl18u250t2_wc 

Number of ports:              107
Number of nets:               684
Number of cells:               16
Number of references:          16

Combinational area:       914255.375000
Noncombinational area:    1185083.125000
Net Interconnect area:      undefined  (No wire load specified)

Total cell area:          2099769.500000
Total area:                 undefined


This is without memories, about 2 mm^2 standard cell area, and divided by 12.2,
the area of a 2-input NAND/NOR gate, it is about 172 kGates (NAND equivalent). 
The design contains about 10000 D-FlipFlops.

A frequency of 50 MHz (without memory tming or external timing constraints) is easily met.