---------------------- Code Version 2.3 from April 2009. (Cumulative release incorporating 2.1-2.3 changes) ---------------------- Major changes in 2.3: - All configurations are supported by generates rather than multiplexing. All synthesis tools support generates therefore it is better to do so. - Set Receive reset and system reset as active low (Note: all designs should set RST_N low to reset the spwrlink component). - Fixes all known issues with version 2.0 - Testbench updated with new VHDL testbench methods. Functional specification document is added for test-bench clarity. Testbench runs all configurations in a loop checking each possible configuration of pipeline, double data rate, slowclk_10mhz and each bitclock configuration, 80 configurations in total plus 3 additional configurations. This creates a longer but more complete testbench run. A short list of the test-bench additions is listed below: * Order command files so they relate to each section of the SpaceWire standard which is cross referenced in the specification document. Therefore there is a command file for signal level, character level, etc. * Add command files which support different clock rates for each type of transmit bit clock configuration. These command files are named with the configuration settings they control. * Add command files which relate only to the bit rate and timing generation of each configuration of the CODEC. * Signal checking of each UUT signal can be performed using UUT_Status. * Data and time-code checking is performed automatically, through command, by uut_data_check and uut_tick_check. Failure is detected and causes assert failure in test-bench * Additional tests in the testbench are: + T.CHA.14 - Transmit time-code in run state + T.EXC.1,2 - Automatic check for test case + T.EXC.ERW.2 - Automatic check for test case + T.EXC.RDY.2 - Automatic check for test case + T.IF.RBUF.1 - Receive buffer interface test case + T.IF.RBUF.2 - Receive buffer interface test case + T.IF.RBUF.3 - Receive buffer interface test case + T.IF.RBUF.5,6 - Receive buffer interface test case + T.IF.RBUF.8 - Receive buffer interface test case + T.IF.STAT.all - Status interface test case + T.IF.SYSCLK.1.a T.IF.SYSCLK.2.a T.IF.TXCLK.1.a T.IF.TXCLK.2.a + T.IF.SYSCLK.1.b T.IF.SYSCLK.2.b T.IF.TXCLK.1.b T.IF.TXCLK.2.b + T.IF.SYSCLK.1.b T.IF.SYSCLK.2.b T.IF.TXCLK.1.b T.IF.TXCLK.2.b - Clock rate with dividers test cases + T.IF.TBUF.1 T.IF.TBUF.2 - Transmit buffer interface test cases + T.IF.TBUF.3.a - Transmit buffer interface test cases + T.IF.TBUF.3.b - Transmit buffer interface test cases + T.PERF.1 - Performance test case Notes: - Some versions of modelsim require the vsim -novopt option to run the simulation successfully. This is due to a Modelsim bug which is fixed in Modelsim 6.4 File Changes: top/spwrlink.vhd ================ Cause: Unused signals Fix: Remove unused nchar resync signals in spwrlink.vhd. rxnchar_resync component can only be implemented with flip-flops Operation/Interfaces: No changes required to operation or interfaces. Cause: RTAX devices use active low reset. Other commercial implementations usually support both. Fix: Active low reset at top level (RST_N input port) Operation/Interfaces: User must change input reset to be active low top/spwrlink_pkg.vhd ==================== Cause: Time-codes are not discarded by the time-code send component when requested to send a time-code and the link is not running. This is not what the user might expect when following the SpaceWire standard. Fix: Add configuration option for processing of TICK_IN when the link is not active. The configuration signal CFG_TICK_KEEP has the following meaning. CFG_TICK_IN_KEEP=0 Time-codes are discarded if the link is not active CFG_TICK_IN_KEEP=1 Time-codes are retained until the link starts or another TICK_IN is performed Operation/Interfaces: The default setting discards time-code so it is different from the previous default Cause: When DDR mode and SLOWCLK are used, SLOWCLK must be set to 5 MHz. This gives poor accuracy on the disconnect and initialisation state machine timeouts (+/- 100 ns). Fix: Add support to set SLOWCLK to 10MHz even when double data rate mode is used. Previously when DDR mode is used SLOWCLK is set to 5MHz which gives poor accuracy for the disconnect and exchange timers. Internally generate 5MHz clock from 10MHz input using toggle flip-flop. The configuration name is CFG_SLOWCLK_10MHz and can be set to 1 to input a 10 MHz clock even when DDR mode is used. Operation/Interfaces: Must change SLOWCLK to 10MHz when CFG_SLOWCLK_10MHZ=1. Setting CFG_SLOWCLK_10MHz=1 creates an additional clock network in txclk_divider.vhd as DDR requires a clock period of 5MHz for the default 10MHz startup rate. transmit/txencode.vhd ===================== Cause: The Xilinx XST synthesizer cannot synthesise some procedures correctly. Fix: Removed load and shift procedures from txencode and replaced the procedure calls with the actual logic. XST and some other synthesisers couldn't handle the procedures. Operation/Interfaces: No changes required to operation or interfaces. Cause: On power up active low reset is better for the transmitter as the transmitter reset DISABLE_TX_N is likely to be zero (guaranteed on some FPGAs). RTAX devices only support active low reset on the device flip-flops Fix: Active low synchronous reset Operation/Interfaces: No changes required to operation or interfaces. Cause: Simultaneous transitions on data/strobe Fix: Fix a boundary case in txencode when DISABLE_TX_N_SYNC(0) is set low for a small number of cycles (less than 3). When this is the case SOUT_CLR_N and DOUT_CLR_N are not set correctly therefore simultaneous transitions can occur on the data strobe outputs. This has not been seen on any devices but was caught in the SpaceWire CODEC testbench by chance. The Spacewire CODEC testbench is updated so it performs reset and link disable at increasing time increments so the data strobe outputs reset and are disabled at different time intervals over a short period from reset Operation/Interfaces: No changes required to operation or interfaces. transmit/txtcode_send.vhd ========================= Cause: Time-codes are not discarded by the time-code send component when requested to send a time-code and the link is not running. This is not what the user might expect when following the SpaceWire standard. Fix: Add configuration option for processing of TICK_IN when the link is not active. The configuration signal CFG_TICK_KEEP has the following meaning. CFG_TICK_IN_KEEP=0 Time-codes are discarded if the link is not active CFG_TICK_IN_KEEP=1 Time-codes are retained until the link starts or another TICK_IN is performed Operation/Interfaces: The default setting discards time-code so it is different from the previous default transmit/txddrreg.vhd ===================== Cause: RTAX devices support active low reset Fix: Active low reset and simplified DDR output encoding with clock enables for rising and falling edges. Operation/Interfaces: No changes required to operation or interfaces. transmit/txddrreg_noenable.vhd ============================== Cause: DDR output with clock enables requires considerable placement effort by the design engineer. When no enables are present the clock can be used directly as the selection of the DDR output multiplexer. Fix: Simple DDR output multiplexer controlled by input clock selecting between two data inputs. Used when a transmit clock configuration which has no enable pulses is used (SYS_DEFAULT, SYS_SLOWCLK, SYS_SLOWCLK_DIV, SYS_DIV, TXCLK_DEFAULT, TXCLK_SLOWCLK, TXCLK_SLOWCLK_DIV, TXCLK_DIV) Operation/Interfaces: User must select correct model when implementing the design. txclk/txclk_en_gen.vhd ===================== Cause: In configurations SYS_EN and TXCLK_EN, and when CFG_DDROUT=1 an incorrect data rate is generated when all TXRATE bits = 1. Fix: Fixed bug in txclk_en_gen. Check for falling edge enable using all count bits. Handles case when TXRATE=(others => '1') Operation/Interfaces: No changes required to operation or interfaces. Cause: Asynchronous reset of clock generation flip-flops is incompatible with the requirement for "no simultaneous transitions" in the SpaceWire standard. Fix: Change to Active low synchronous reset of counter and other flip-flops. Reset must be synchronous as there cannot be an asynchronous reset and a controlled reset of data/strobe Operation/Interfaces: No changes required to operation or interfaces. txclk/txclk_divider.vhd ======================= Cause: Asynchronous reset of clock generation flip-flops is incompatible with the no simultaneous transitions requirement for SpaceWire. Fix: Change to Active low synchronous reset of counter and other flip-flops. Reset must be synchronous as there cannot be an asynchronous reset and a controlled reset of data/strobe Operation/Interfaces: No changes required to operation or interfaces. txclk/txclkgen.vhd ================== Cause: Asynchronous reset of clock generation flip-flops is incompatible with the no simultaneous transitions requirement for SpaceWire. Fix: Change to Active low synchronous reset of counter and other flip-flops. Reset must be synchronous as there cannot be an asynchronous reset and a controlled reset of data/strobe Operation/Interfaces: No changes required to operation or interfaces. Cause: When DDR mode and SLOWCLK are used, SLOWCLK must be set to 5 MHz. This gives poor accuracy on the disconnect and initialisation state machine timeouts (+/- 100 ns). Fix: Add support to set SLOWCLK to 10MHz even when double data rate mode is used. Previously when DDR mode is used SLOWCLK is set to 5MHz which gives poor accuracy for the disconnect and exchange timers. Internally generate 5MHz clock from 10MHz input using toggle flip-flop. The configuration name is CFG_SLOWCLK_10MHz and can be set to 1 to input a 10 MHz clock even when DDR mode is used. Operation/Interfaces: Must change SLOWCLK to 10MHz when CFG_SLOWCLK_10MHZ=1. Setting CFG_SLOWCLK_10MHz=1 creates an additional clock network in txclk_divider.vhd as DDR requires a clock period of 5MHz for the default 10MHz startup rate. initfsm/init_fsm.vhd initfsm/initfsm_counter.vhd =========================== Cause: When DDR mode and SLOWCLK are used, SLOWCLK must be set to 5 MHz. This gives poor accuracy on the disconnect and initialisation state machine timeouts (+/- 100 ns). Fix: Add support to set SLOWCLK to 10MHz even when double data rate mode is used. Previously when DDR mode is used SLOWCLK is set to 5MHz which gives poor accuracy for the disconnect and exchange timers. Internally generate 5MHz clock from 10MHz input using toggle flip-flop. The configuration name is CFG_SLOWCLK_10MHz and can be set to 1 to input a 10 MHz clock even when DDR mode is used. Operation/Interfaces: Must change SLOWCLK to 10MHz when CFG_SLOWCLK_10MHZ=1. Setting CFG_SLOWCLK_10MHz=1 creates an additional clock network in txclk_divider.vhd as DDR requires a clock period of 5MHz for the default 10MHz startup rate. Cause: Initialisation state machine timeouts can vary considerably as the counter is reloaded to stop it counting down. When a seperate SLOWCLK is used as a reference the loading must be acknowledged so some clock cycles may be consumed while moving from Ready -> ErrorReset. Fix: In initfsm_counter when a load is performed, count down to zero, set the event bit and then wait for the next load. Operation/Interfaces: No change receive/rxdecode.vhd ==================== Cause: The receive has an issue where data characters, time-codes and FCTs can still be output from the receiver after an error has occurred and before the receiver is reset by the initialisation state machine. Fix: Receiver now moves to a "receiveError" state where it cannot detect characters until reset by the initialisation state machine Operation/Interfaces: No data characters are output if the receiver has detected an error such as parity or escape error. receive/rxdiscerr.vhd ==================== Cause: When DDR mode and SLOWCLK are used, SLOWCLK must be set to 5 MHz. This gives poor accuracy on the disconnect and initialisation state machine timeouts (+/- 100 ns). Fix: Add support to set SLOWCLK to 10MHz even when double data rate mode is used. Previously when DDR mode is used SLOWCLK is set to 5MHz which gives poor accuracy for the disconnect and exchange timers. Internally generate 5MHz clock from 10MHz input using toggle flip-flop. The configuration name is CFG_SLOWCLK_10MHz and can be set to 1 to input a 10 MHz clock even when DDR mode is used. Operation/Interfaces: Must change SLOWCLK to 10MHz when CFG_SLOWCLK_10MHZ=1. Setting CFG_SLOWCLK_10MHz=1 creates an additional clock network in txclk_divider.vhd as DDR requires a clock period of 5MHz for the default 10MHz startup rate. Cause: The disconnect period can exceed 1 us when SLOWCLK is 5 MHz, and CFG_SLOWCLK_10MHZ=0. This is due to a missing clock enable on one of the disconnect detection flip-flops. Fix: Fix receive disconnect method where SLOW_EN clock enable should be used to qualify DISC_ERR_i. Operation/Interfaces: Disconnect is not detected after 1 us. When 5 Mhz SLOWCLK is used then the timeout period is 800-1000ns. Cause: A flip-flop whose output feeds into the initialisation state machine is asynchronously reset by the initialisation state machine therefore creating a path from the initialisation state machine flip-flop, through the asynchronous reset and to the setup time of the desintation initialisation state machine. Fix: Break the reset path by resetting the system clock flip-flops with RST_N Operation/Interfaces: Timing analysis does not report the reset path. other/clkmux.vhd ================ Cause: Asynchronous reset cannot be used as this could cause glitches on the data/strobe outputs. As no reset is used the flip-flops require a few clock cycles to reach a steady state. These cycles are consumed when the transmitter is not doing anything so glitches cannot occur. Fix: clkmux flip-flops cannot be reset but they reach a stable state after start-up when the transmitter is disabled. Operation/Interfaces: No simultaneous transitions occur. -------------- Code Version 2.0 from December 2005. -------------- Major changes in uodcode_cvsrel_2_0 Fixed dropped empty packets credit error bug Fixed state machine timing errors Removed latch configuration for receive character resynchronisation * top/spwrlink.vhd =================== - Cause : When empty packets were received (i.e. EOP/EEP followed by EOP/EEP) the receive credit counter was not updated properly. For example, if consecutive EOP/EEP were received, the Rx credit counter was incremented only once. The Tx credit counter at the sending end of the link would have been incremented once for each EOP/EEP. This would result to a discrepancy between the two FCT counters. If many empty packets were sent the link might slow down. If 32 empty packets were sent the link would stop. - Fix : Added rxdataformat component to format empty packets and end of packet markers (EOP/EEP) from the rxdecode component so they can be taken into account properly by the receive credit counter. - Operation/Interfaces : No changes required to operation or interfaces. - Cause : rxnchar_resync_latch configuration removed as it is not compatible with the rxdataformat component. - Fix : As above - Operation/Interfaces : No changes required to operation or interfaces. * top/spwrlink_pkg.vhd ======================= - Cause : Added TIMING_6_4 and TIMING_12_8 constants for finer control of the 6.4us and 12.8us state machine timer timeouts. - Fix : As above. - Operation/Interfaces : No changes required to operation or interfaces. * initfsm/initfsm_counter.vhd ============================== - Cause : Constants c6_4usval, c6_4usval_ddr, c12_8usval and c12_8usval_ddr removed and replaced by constants TIMING_6_4 and TIMING_12_8 in spwrlink_pkg.vhd for finer control of the 6.4us and 12.8us timer. - Fix : As above - Operation/Interfaces : No changes required to operation or interfaces. - Cause : If an error (RxErr) was detected at the end of ErrorWait, but the 12.8us timer expiry event had been issued, then the state machine would move to state ErrorReset, receive the timer event and move straight to ErrorWait again, therefore violating the 6.4us timeout interval (from ErrorReset to ErrorWait). - Fix : TIMER_EVENT only issued when not trying to load a value into the counter. - Operation/Interfaces : No changes required to operation or interfaces. * initfsm/init_fsm.vhd ======================= - Cause : Bug found where the timer is not restarted when moving from state ErrorWait to ErrorReset. This will cause the ErrorReset time to be set to the remaining time ErrorWait timeout time (i.e. 12.8us+-10% - 0us) and therefore violate the 6.4us +-10% time. - Fix : Enabled state machine output load6_4 when moving from state ErrorWait to state ErrorReset. - Operation/Interfaces : No changes required to operation or interfaces. - Cause : Bug found where a time event could occur just as a value is loaded into the 6.4/12.8us counter (see initfsm_counter changes). - Fix : Timer event is not enabled when trying to load a value into the state machine counter. - Operation/Interfaces : No changes required to operation or interfaces. * receive/rxdecode.vhd ==================== - Cause : Empty packets are not dropped in the rxdecode block as they must be taken into account by the receive credit counter (i.e. an EOP/EEP is still an Nchar). - Fix : GOT_CHAR output added and NEXT_CONTROL bit added for received data formatting. - Operation/Interfaces : No changes required to operation or interfaces. * receive/rxdataformat.vhd ======================== - Cause : Empty packets were dropped in the receiver component receive/rxdecode.vhd and were not taken into account by the rxcredit counter (component receive/rxcredit.vhd). Empty packets cannot be passed directly to rxcredit counter as the expected data rate and empty packet rate do not match, i.e. an empty packet rate of 50MHz can be observed for an input bit rate of 200MBit/s whereas the normal data rate is expected to be around 20MHz for data packets. - Fix : End of packets/Empty packets are formatted in the receive clock domain in the added component receive/rxdataformat.vhd. Empty packets are passed to the rxcredit counter block in twos so the maximum empty packet rate into the receiver credit counter is 25MHz. An extra receive clock cycle latency is added to data characters as they are passed through the rxdataformat block. - Operation/Interfaces : No changes required to operation or interfaces. * receive/rxcredit.vhd ==================== - Cause : Mofified receiver credit counter to accept empty packets from the rxdataformat block. - Fix : As above - Operation/Interfaces : No changes required to operation or interfaces. * receive/rxnchar_resync_ff.vhd ==================== - Cause : Formatting the received data into end of packets and normal data characters is now performed in rxdataformat making rxnchar_resync_ff.vhd a straight forward asynchronous memory - Fix : As above - Operation/Interfaces : No changes required to operation or interfaces. * transmit/txencode.vhd ===================== - Cause : Active low reset is preferable for transmitter flip-flops to avoid startup pattern after reset. - Fix : Active low reset for transmitter signal DISABLE_TX changed to DISABLE_TX_N - Operation/Interfaces : No changes required to operation or interfaces. * txclk/txclkgen.vhd ===================== - Cause : An extra configuration selection is required between the divided bit clock and the clock enable generator bit clock at the output of the txclkgen module. Note these selection multiplexers are optimised at synthesis due to the constant signal which is performing the multiplexing. The extra selection is included to ensure simulation results are correct as the delta delays for clock signal assignment and clock enable signal assignment must be matched. - Fix : Extra configuration selection added. - Operation/Interfaces : No changes required to operation or interfaces. ---------------------- ++ uodcodec_cvsrel_1_4 ---------------------- receive/rxnchar_resync_ff.vhd ============================= + Storage for received n-char resynchronisation in flipf-flops implemented as in VHDL as inference of RAM. This causes problems when discrete flip-flops are synthesised as the output multiplexer to the output register of the storage is not tolerant to glitches which occur as data is written to storage on receive clock and captured in output register on receive buffer clock. Use data enabling method as used in rxnchar_resync_latch.vhd to capture storage data in output register. A simple inference file called receive/rxnchar_resync_ffstore_inferfpgaram.vhd is added for users who want to infer RAM to save area. No changes required to operation or interfaces. transmit/txencode.vhd ===================== + Some synthesisers have problems with the parity assignment in load_[char] procedures where the parity bit is assigned to a value dependent on the character loaded and used to determine the outgoing characters parity value. As the parity bit was assigned first the synthesiser inferred it was a constant value and removed the parity bit register. Move the parity assignment after the usage and the synthesiser does not remove the parity bit No changes required to operation or interfaces tramsit/txddrreg.vhd ==================== + Better alignment of DDR output multiplexer select signal (see CODEC user manual for usage) As above. No changes required to operation or interfaces. ---------------------- ++ uodcodec_cvsrel_1_3 ---------------------- rxcredit.vhd ============ + When error recovery is performed then RX_CREDIT_ERROR is reported incorrectly if data is present on the receiver N-char synchronisation buffer. On error recover the FCTPTR is set the value of the WRPTR therefore no data characters are expected but some data characters may not be Count four clock cycles so received N-char sync buffer can be cleared before FCTPTR is set to WRPTR. No changes required to operation or interfaces rxdecode.vhd ============ + FIRST_NULL is asserted incorrectly when last portion of FIRST_NULL character is incorrect, even though rxdecode state machine does no recognise the NULL character. i.e. 01110100bb11. Bits bb are checked by the state machine but not by the FIRST_NULL output. If first NULL is asserted incorrectly then state machine will instruct transmitter to send FCTs and therefore other end of link will move to state Run. If another good NULL is not received then the link will be disconnected and both ends will move to state ErrorReset. FIRST_NULL only asserted when moving from state firstNullFctCode00 to state nibble1. No changes required to operation or interfaces rxnchar_resync_latch.vhd ======================== + RXCLK_WREN(0) is used incorrectly as write enable to latches. RXCLK_WREN(1) should be used. Race conditions may occur when an EOP is received directly after data as data will not be held valid for a full receive clock cycle. Assign RXCLK_WREN(1) as gate enable to latch cells No changes required to operation or interfaces