14-July-2004:

The release 1.2 is available, providing the following enhancements:

- A patch providing registered FIFO full/empty bits. 
  This patch will improve timing on the AMBA bus.

- Along with the known Austrian Aerospace testbench, the Astrium-Velizy test
  environment from the SCOC contract is now provided as described in the
  documents. This testbench relies on some (Modelsim-)precompiled packages.

- Compile scripts allowing either a complete recompile with makefile
  generation, or a re-make (if makefiles exist).

- Synthesis setup for the complete IP (including amba), or the version without
  amba interface.

Release Notes: 

- It was reported by W. Ogiers from FillFactory that the Austrian Aerospace 
  testbench uses the definitions of EOP and EEP at character level (i.e. 101 for EOP), 
  rather than the host interface recommendation in the standard (EOP = all data bits 0).
  The spacewire IP itself only looks at bit 0 of the FIFO and then generates the correct 
  sequence (P101) on the serial lines. However, if you want the behavioural AAE spacewire
  device to generate an EOP, you will have to send a '101' to the FIFO with
  the command SPWR TRANSMITBYTE 5 

- It was reported by W. Ogiers from FillFactory that the design contains
  Flip-Flops whose asynchronous reset is driven by internal signals. This may
  cause problems at scan test and require bypass multiplexers to be inserted,
  either at source code level, or at test/scan insertion (see Synopsys command
  insert_dft). 10 August 2004