------------------------------------------------------------------------ September 2006: A bug has been reported in the write protection unit (wprot.vhd): It is not possible to operate both protection units simultaneously in "block-allow" mode (i.e., both bp bits cleared), unless there is overlap between the segments defined in the two units. The reason is that the errors generated by both units are simply OR'ed, which means that even if one area allows the writing (hit inside allowed segment), the other area will still generate a trap. A workaround to obtain two "allowed" areas is to configure one large allowed area with one write protect unit and bp = 0, and inside this area, configure a small forbidden area with the other unit in block protect mode (bp = 1). A fix for this unintended behaviour will be included in the next release. ------------------------------------------------------------------------ 15. June 2005: The following functional problems have been reported with the LEON2FT VHDL model or its documentation: 1) Wrong PC stored during FPU exception trap. Instead of storing the current and new program counters (PC and NPC), an FPU exception trap stores twice the NPC, making it impossible to reexecute the trapped instruction. Not relevant in applications, since a trapped FPU instruction is not normally retried (would lead to the same trap again). 2) Single-stepping over SWAP and LDSTUB instruction locks AHB bus. As the DSU and the processor communicate with the same bus, trying to step through multicycle atomic instructions (locking the bus for 2 cycles) leads to a system lockup requiring a reset. These instructions are not generated by compilers, and the problem is not normally seen by users. 3) Divide overflow will not clear zero flag, yet the overflow is correctly flagged. As long as application software checks overflow condition before any further processing of the result, as it is usually done, this bug is not harmful. 4) There is a discrepancy between the register file fault-injection as it is implemented in the default configuration when the model is shipped, and the respective description in the user manual. This is not relevant in application, however may be seen by users who do diagnostic fault injection to test the register file EDAC's. An update of the model and/or documentation is under way. ------------------------------------------------------------------------ LEON-2 FT VHDL model, version 1.0.9.7, released 06 January 2005 Updated FPU parallel interface (leon/iu.vhd, leon/iface.vhd, leon/debug.vhd) * EDAC errors detected in the FP register file can be signaled through the parallel FPU interface to the IU. Instruction restart capability for FP instructions executing in parallel with the IU is added. * Added VHDL debug support for the FPU parallel interface. Register writes and disassembly of the FP instructions executing in the parallel FPU interface can be printed out in the VHDL simulator console. Added GRFPU-wrapper component declaration and instantiation (leon/proc.vhd) and added GRFPU to FPU core type (leon/target.vhd). Fixed a bug in the memory controller (leon/mctrl.vhd). If both SRAM and SDRAM where used, an access to SDRAM caused wrong SDRAM memory position to be accessed if the operation was preceded by an access to the SRAM. Fixed a bug in the serial FPU interface (leon/iu.vhd). CALL instruction could write the value of the PC in a floating-point register instead of %o7. This happened if the CALL was to an address whose offset from the CALL instruction was more then 2 MB. ------------------------------------------------------------------------ Note for FPGA compilation (18. June 2004): LEON2FT in all its current versions is not synthesisable with Xilinx XST. If you want to synthesise LEON2 for Xilinx with this tool, please download one of the leon2-xst versions from www.gaisler.com ------------------------------------------------------------------------ LEON-2 FT VHDL model, version 1.0.9.6, released 01 June 2004 A bug in the LEON2 divider has been fixed, which caused the divided value to be wrong for certain negative operands. Updated file: div.vhd The divider is only used when the V8 flag is given to the compiler, so if this flag is not set the divider is not used and the error is not seen. However, without the V8 flag, the multiplier is also not used which some users might object to. Updated tracelines to 512 in device_virtex2_nopci.vhd to agree with AT697 config. The following changes only concern users of the PCI4LEON interface (Insilicon core): Correct outcommented line 383 in leon_pci.vhd (pci_lock_in_n -> pci_lock_n) Modified active-high pci_host signal to active low pci_sysen_n signal. Updated files: leon_pci.vhd, iface.vhd, tbench/leonlib.vhd, tbench/tbgen.vhd. It will only work with releases AFTER 3.3e of this package. ------------------------------------------------------------------------ LEON-2 FT VHDL model, version 1.0.9.5, released by ESA, 26 August 2003 * Note that leon2ft-1.0.9.5 is functionally closest to leon2-1.0.13. * Besides the SEU fault tolerance, which is described in a document * separately available from ESA, this model differs from the free * (LGPL) leon2-1.0.13 distribution by the 'doubled PROM waitstates' * feature (see below under 'fix-2'). The following fixes with respect to the previous release (leon2ft-1.0.9) have been included into this release: fix-1, 30-January-2003: ------------------- Added LEON patch leon/iu.vhd (original file leon/iu.org) * Improved timing path in interrupt prioritisation * Remove possibility of generating a spurious interrupt when psr.et and psr.pil are changed at the same time. * Updated cache.c and recompiled test benches so that the test bench can handle any cache configuration." fix-1a, January/February 2003 and later: ------------------- Fixes in tech_atc18.vhd and tech_map.vhd provided by Atmel Fixed dual-port RAM instantiation in tech_virtex2.vhd Added leon/device_virtex2_nopci.vhd Added synthesis configuration syn/lexil.* for virtex2 synthesis (without PCI) Added FT version of the SDRAM memory model, able to generate checkbits (mt48lc16m16a2.vhd). fix-2, 02-April-2003: ------------------- Updated leon/mctrl.vhd on 02-April-2003 * Implements the doubled waitstates for the PROM interface. With the same register bits, * now waitstates can be adjusted 0, 2, 4, 6, .. 30 instead of 0, 1, 2, 3, .. 15. The original file is renamed to mctrl.vhd.1ws fix-3, 23-May-2003: ------------------- Investigating a problem report from a customer, we have found bug in the cache flush mechanism. There existed a very unlikely (but yet possible) chance that after flushing the caches, a false hit would occure. The problem only existed in multi-set caches. Updated files in subdirectory leon: cachemem.vhd dcache.vhd icache.vhd iface.vhd fix-4, 18-Jun-2003: ------------------- Updated dcache.vhd which solves a recently discovered bug in snooping. Also, the leon_full test bench has been updated to disable the cache until cache ram has been initiated as proposed by Roland. fix-5, 26-Aug-2003: ------------------- Updated LEON source code: Updated dcom_uart.vhd to improve automatic baud-rate generation in the DSU uart. Some hosts (in particular Sun stations) could not synchronize with the previous implementation. Updated configuration setting to traceline size = 512 (from previously 256) Updated iu.vhd to fix the following bugs: 1.) SWAPA instruction which previously was not trapping on unaligned address error (omission in a case statement). This trap condition is not tested in the sparc test suite, and it is not used in any known operating system (12th Aug 2003). 2.) A sequence of LD/MULSCC could fail if a load dependency existed but the load data was not used by MULSCC due to Y[0] = 0. This bug is not tested by the Sparc test suite, and the combination LD/MULSCC not used in C-compiled programs (22nd Aug 2003). Updated test benches/programs: --------------------------------- iram.vhd memory initialised to 0 to fix gate simulation problems mspram.vhd fixed falling-edge write to rising-edge as it should be tb_msp.vhd added data bus keeper to ensure sufficient write hold-time at RTL level Updated msp test sequence (added fpu tests and a few more modifications) ------------------------------------------------------------------------ LEON-2 VHDL model version 1.0.9, released on 2 December 2002 * New features: - Improved dcache hit timing for multi-set configurations - New config option for optimised dcache read/write timing * Bug fixes: - WRPSR did not disable interrupts for the next instruction, potentially causing error traps if WRPSR canged psr.et from 1 to 0, psr.pil /= 15, and an interrupt occured at the same clock cycle. - Store FPU status reg (STFSR) failed due to incorrect timing optimisation introduced in leon2-1.0.8 (iu.vhd). - Caches worked only if number of icache sets >= dcache sets * Other fixes (non-critical) - Cache test program failed on certain cache configurations. - Fill icache line to end-of-line even if program branches - Documentation update regarding write-protection functionality ------------------------------------------------------------------------ LEON-2 VHDL model version 1.0.8, released on 24 November 2002 * New features: - Set-associative cache with random, LRR or LRU replacement - Cache-line locking - Pipelining option on 16x16 integer multiplier - Atmel ATC18 (0.18 um) port - Virtex2 port - Support for on-chip ram * Bug fixes: - DSU access to cache rams could fail under rare conditions - DSU AHB breakpoints only worked in configurations with trace buffer - SDRAM controller could not handle AHB bursts ended with HTRANS_BUSY ------------------------------------------------------------------------ LEON-2 VHDL model version 1.0.7, released on 18 September 2002. (J.Gaisler) * SDRAM controller generated wrong column address for sdrams with more than 10 column address bits. * Fixed minor re-arbitration bug in PCI arbiter ------------------------------------------------------------------------ LEON-2 VHDL model version 1.0.6, released on 30 August 2002. (J.Gaisler) * WRY intruction was priviledged but should not be (iu.vhd) * Improved version of Actel Axcellerator FPGA port (tech_axcel.vhd) * New RTL multipliers to improve simulation time (multlib.vhd). * Modify tkconfig/Makefile to also work with solaris make. * Modify mkdevice.c in tkconfig to generate device.vhd such that a bug in Leonardo is avoided. ------------------------------------------------------------------------ LEON-2 VHDL model version 1.0.5, released on 25 July 2002. (J.Gaisler) * Various UART improvements: - Extended baud-rate range + better baud-rate detection in DSU UART - Added 8-bit glitch filter in UART receiver - Fixed potential loss of received character (under rare conditions) * Timing improvment in the ATC25 port * Improved DSU timer accuracy during single-stepping * SMUL/UMUL could under some (very rare) condiditions return a result even if pipeline was flushed due to trap/interrupt. * SWAP instruction only wrote odd registers * tkconfig used icache parameters also for dcache * Miss-aligned access trap changed to have higher priority than FP exception caused by unimplemented STDFQ. (This is just to be fully compliant to SPARC V8, has no practical meaning). * Behavioural regfile (generic_regfile_iu) used wrong read address for port 2 when generic_dpram_as was used (tech_generic.vhd). * Removed unnecessary write-bypass in generic_regfile_iu (tech_generic.vhd) * Re-structured the test benches (see manual) ------------------------------------------------------------------------ LEON-2 VHDL model version 1.0.4, released on 6 July 2002. (J.Gaisler) * Y register not properly updated after SMUL/UMUL instruction * UART loop-back CTSN/RTSN cross-strap needen one more fix. * Uninitialised variable in acache.vhd caused unnecessary latches to be infered * Register file power-down support for ATC25 added ------------------------------------------------------------------------ LEON-2 VHDL model version 1.0.3, released on 1 July 2002. (J.Gaisler) * Added preliminary Actel Proasic FPGA port * Added (very) preliminary Actel Axcelerator FPGA port * Made register file power-save optional to avoid timining problems on some targets. * tkconfig: - perform more sanity checks - set default frequency to 25 MHz in tkconfig to avoid false out-of-range errors with a certain synthesis tool. - did not set rftype - fixed - fixed various cygwin problems in mkdevice.c, the generated device.vhd should now be correct on all platforms ------------------------------------------------------------------------ LEON-2 VHDL model version 1.0.3beta3, released on 15 June 2002. (J.Gaisler) * Added GUI-based configuration tool (tkconfig) !! * Various documentation updates and corrections * Fixed wrong address for ICLEAR2 in testbench (tsource/leon.h) * updated leon/bprom.vhd to latest version (Christian) * updated pmon/lmon.o * Extended configuration to allow caches up to 2x64 Kbyte * Made clock generator (clkgen) tech-specific to allow target-specific clock generation (PLL ...) * Removed gated-clock option and cleaned-up clk/reset generation * Added optional PCI reset synchronisers * Added alternative Virtex regfile implementation (rftype=2) with improved write timing. * UART loop-back mode did not cross-strap CTSN/RTSN - fixed. * tech_generic did not work without infer_pads - fixed. * tech_virtex did not work *with* infer_pads - fixed. ------------------------------------------------------------------------ LEON-2 VHDL model version 1.0.3beta2, released on 6 June 2002. (J.Gaisler) * Modified SDRAM bank address to always appear on A[16:15] * Modified SDRAM bank size field in memory config register 2 ------------------------------------------------------------------------ LEON-2 VHDL model version 1.0.3beta1, released on 31 May 2002. (J.Gaisler) * Added PC100/PC133 SDRAM controller * Modified AHB arbitration rules to grant a low-priority master if a high-priority master drives htrans with idle * drive HPROT to all AHB slaves * fix uart debug 'stuttering' at high frequencies * avoid clearing irq pending bits when clearing irq force bit (irqctrl.vhd) * Feed-back from write strobes to data bus drivers is made optional in the configuration record. * Removed the 'raw-address' option - nobody used it anyway .. * Merged port to TSMC 0.25 um with Artisan rams (contrib. by Daniel Mok) * Clean up reset generation and removed un-necessary 'rawrst' signal. ------------------------------------------------------------------------ LEON-2 VHDL model version 1.0.2a, released on 25 February 2002. (J.Gaisler) * UMAC/SMAC erronously updated ASR18 when trapped (fixed). ------------------------------------------------------------------------ LEON-2 VHDL model version 1.0.2, released on 20 February 2002. (J.Gaisler) * Corrected ASI generation during co-processor load/store * Timing optimisation of data cache AHB/HLOCK generation * Timing optimisation of data cache hit generation * Modification of configuration record to work-around Leonardo-2001.x bugs. * Improve accuracy of DSU timer during stepping * DSU did not break on load exception (trap 0x09) (fixed) * Change back to cacheability table (acache.vhd) * Remove all use of non-standard HCACHE signal (amba.vhd, acache.vhd) * Add generation of AHB HPROT signals for processor (acache.vhd) * Modified access with ASI 4 and 7 to force a miss but not allocate a new line * HSIZE was incorrectly set to 8-/16-bits during byte/halfword cacheable loads when the cache controller in fact expected a 32-bit word (fixed, acache.vhd). * Fixed broken disassembly when the DSU is not enabled * Added modelsim-specific macro for top-level compile (modelsim/compile.do) ------------------------------------------------------------------------ LEON-2 VHDL model version 1.0.1, released on 15 February 2002. (J.Gaisler) * Addition of a partially completed IEEE-754 floating-point unit, contributed by Martin Kasprzyk from Lund Technical University * Modification of AHB arbiter re-arbitration policy (again). Re-arbitration is now blocked during locked or burst transfers. * Correction of AHB arbiter's sampling of the HLOCK signal * Processor did not handle AHB retry properly on certain load/store operations (fixed) * Dummy drivers on unused AHB/APB slave signals used wrong bus index (fixed) ------------------------------------------------------------------------ LEON-2 VHDL model version 1.0.0, released on 7 February 2002. (J.Gaisler) * Addition of on-chip debug support (dsu, dsu_mem, dcom, dcom_uart) * Addition of data cache snooping for Virtex and ATC25 targets * Modification of AHB arbiter bus arbitration * Fixed problem with multiple break detection in UART (uart.vhd) * Reading the baudrate register in UART returned scaler (uart.vhd) * Various area/speed optimisations (iu, dcache) * Added one BRDYN-controlled ram chip select * Various documentation fixes ------------------------------------------------------------------------ LEON-1 VHDL model version 2.4.0, released on 26 November 2001. (J.Gaisler) * PMON erronously cleared preset number of ram waistates * testbench ram did not read last line in program file (reported by Marius Vollmer) ------------------------------------------------------------------------ LEON-1 VHDL model version 2.3.7, released on 12 August 2001. (J.Gaisler) * Cache controllers are now disabled when cache state is set to X0 (was 00). (dcache.vhd, icache.vhd) * Modified 8/16-bit I/O bus handling (see manual) * Corrected BRDYN to only affect I/O area * Moved regfile and cache memories to proc.vhd to get more accurate wire-loads during synthesis ------------------------------------------------------------------------ LEON-1 VHDL model version 2.3.6, released on 24 July 2001. (J.Gaisler) * Finally fixed dual-boot option (thanks to Stephan Schirrmann) * Added UMC 0.18 um port (thanks to Raijmond Keulen) * Fixed default AHB master handling (thanks to Daniel Mok) * Modified the generation of data_storage_error trap (iu.vhd) * Moved regfile from proc to iu * Moved acache from proc to cache * Added separate regfile generator for parallel FPU/CP * Fixed incorrect rounding in integer divider unit * Fixed problem with byte-writes when using 8/16-bit I/O bus * Modified I/O bus cycle to add address lead-in cycle ------------------------------------------------------------------------ LEON-1 VHDL model version 2.3.5, released on 3 July 2001. (J.Gaisler) * Corrected missing I/O pad problem in ATC25 port * Cleaned-up register-file write strobe generation * Modified bprom.c to properly detect 8-bit ram ------------------------------------------------------------------------ LEON-1 VHDL model version 2.3.4, released on 1 July 2001. (J.Gaisler) * Added UMC 0.25 port (FS90/FTC25) (tech_fs90.vhd) * Modified AHB error interrupt generation (ahbstat.vhd) * Simplified ATC25 ram mega cell interface (tech_atc25.vhd) * Added proper PCI pads for ATC25 (tech_atc25, tech_map) * Added more PCI device configuration options (target.vhd) * Fixed missing waitstate in 8-bit memory read cycle (mctrl.vhd) * Added hardware instruction and data watchpoints (iu.vhd) * Cleaned-up the test program boot-strap code (boot*.S) * Gave data_store_error highest trap priority (SPARCV8) (iu.vhd) * Modified pad drive strenght instantiation * D[15:0] can also be used as PIO outputs in 8/16-bit memory mode * Prom bank 1 can now be accessed even if internal boot prom is enabled * Fixed occasionally missed timer restart ------------------------------------------------------------------------ LEON-1 VHDL model version 2.3.3, released on 25 May 2001. (J.Gaisler) * Fixed lost interrupt problem in interrupt controller (irqcrl.vhd) * Corrected wrong length of UART start bit (uart.vhd) * Made pmon/eprom.c compile with LECCS-1.1 ------------------------------------------------------------------------ LEON-1 VHDL model version 2.3.2, released on 22 May 2001. (J.Gaisler) * Added optional secondary interrupt controller * Fixed UART transmitter lost interrupt problem * Updated xilinx .ngo file for PMON ------------------------------------------------------------------------ LEON-1 VHDL model version 2.3.1, released on 13 May 2001. (J.Gaisler) * Updated virtex_prom256.ngo to contain latest PMON * Added utility to put rdbmon in boot-prom on FPGA's * The UART can now optionally be clocked from PIO[3] * Added possibility to use both internal and external boot prom ------------------------------------------------------------------------ LEON-1 VHDL model version 2.3, released on 27 April 2001. (J.Gaisler) * APB peripherals in mcore used wrong clock (thanks Steven!) * UART receiver used wrong irq enable bit (uart.vhd) I fixed this once already but somehow it got lost ...? * ASI mapping: only ASI 8 - 11 are cachable * Added PCI arbiter (thanks to R.Weigand, ESA) * Added hardware multiplier and divider for V8 MAC/MUL/DIV (MAC/MUL work funded by ST, thanks Cosma!) * Re-structured target dependent libraries, only tech_map.vhd needs to be edited to add support for new foundry. * Synplify- and Leonardo-specific packages removed, not needed with synplify-6.2 and leonardo-2001.1a ! * PMON enables both uarts by default ------------------------------------------------------------------------ LEON-1 VHDL model version 2.2.2, released on 3 March 2001. (J.Gaisler) * Added complete synthesis script for synopsys DC (syn/leon.dcsh) * fix problems with 'X' in post-synthesis simulation by letting the test program explicitely initialize the data cache and certain registers (tsource/*.c) * added pull-ups on data bus and I/O port in VHDL test bench (tbench/tbgen.vhd) * work-around for synopsys bug in aggregates (tech_atc35.vhd) * documentation ------------------------------------------------------------------------ LEON-1 VHDL model version 2.2.1, released on 19 February 2001. (J.Gaisler) Additions: * Added regfile and cache ram tests (tsource/ramtest.c) * iram: can use *.dat files produced by both LEONCCS and LECCS Bug fixes: * dcache: LDDF followed by FPOP could corrupt data on cache miss * mctrl: write waitstates for ram/rom used read-ws setting Beauty spots: * timers: wr signal missing in process sensitivity list * documentation ------------------------------------------------------------------------ LEON-1 VHDL model version 2.2c, released on 1 November 2000. (J.Gaisler) Additions: * Flattened hierarchy to simplify addition of AMBA modules * Number of AHB and APB slaves is configured automatically from configuration table * Wacthdog can be supressed in configuration record Bug fixes: * boot-prom (bprom.c) failed to set proper stack pointer * Documentation ------------------------------------------------------------------------ LEON-1 VHDL model version 2.2b, released on 13 October 2000. (J.Gaisler) Additions: * 16-bit memory interface + read-modify-write option * boot-prom with memory auto-configuration Bug fixes: * Documentation ------------------------------------------------------------------------ LEON-1 VHDL model version 2.2a, released on 6 October 2000. (J.Gaisler) Additions: * FPU/Co-processor interface added (iface.vhd, iu.vhd, cp.vhd) * AMBA AHB/APB buses * boot-prom * Synopsys VSS/FC2 support * Leonardo 1999.x support * Xilinx Virtex ram generators Bug fixes: * wong dependency check in MULSCC when icchold enabled * UART receiver used wrong irq enable bit (uart.vhd) * DPRAM168x34 & DPRAM168x39 had only 136 regs (ramlib.vhd) * sregsin missing in decode process sensitivity list (iu.vhd) * Wrong data dependency check when FPU is enabled (iu.vhd) * STF instruction did not check for address alignment error (iu.vhd) ------------------------------------------------------------------------ LEON-1 VHDL model version 2.1, released on 11 May 2000. (J.Gaisler) * Improved timing for FPGA implementations * Added support for bootable cache (Xilinx only) * Added support for ATC35 0.35 cmos process * Removed memory EDAC and cache parity * Added PCI signals and PCI initial support (not completed) ------------------------------------------------------------------------ LEON-1 VHDL model version 2.0, released on 2 February 2000. (J.Gaisler) ------------------------------------------------------------------------ LEON-1 VHDL model version 1.1, released on 14 October 1999. (J.Gaisler) * Added support for Xilinx Virtex FPGA * Added missing contraints file for synplify * Improved simulation models of target specific ram blocks * Fixed false write hit during byte/halfword write (dcache) * Fixed false read hit during flush opration (icache) * Optimised data parity generation (icache, dcache, mctrl, macro) ------------------------------------------------------------------------ LEON-1 VHDL model version 1.0, released on 7 October 1999. (J.Gaisler) ------------------------------------------------------------------------