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Version 0.7 (2015-01-16):
    - Fixed bug in EDAC type 3 (EDAC16Hamming) reported by D. Fiore (TAS-I)
    - Simplified coding style (removed recurrent <= '0' assignments)
    - Improved test bench (assertions, self-checking)
    - Added Makefile and synthesis script
 
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Release 0.6 
Roland Weigand, 19-Aug-2005

This release contains the following updates:

1. Added EDAC57 with single error correction capability,
   using 6 parity bits: Hamming (63,57).
   Includes a C-model of the EDAC57
2. Provided precompiled, encrypted Modelsim library
 
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Release 0.5 
Roland Weigand, 11-Jul-2002
Sandi Habinc, 20-Nov-2002

This release CONTAINS the following updates:

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Following a bug report in the 64 bit EDAC from lars.ericsson@xelerated.com, 
submitted 30 Jan 2002, the following patch was applied to edac.vhd:
REPLACE (starting line 3345)

--      CheckOut(2)   <=  not (DataOut(0)  xor DataOut(1)  xor DataOut(5)  xor
--                             DataOut(6)  xor DataOut(7)  xor DataOut(11) xor
--                             DataOut(12) xor DataOut(13) xor DataOut(16) xor 

WITH:

      CheckOut(2)   <=  not (DataOut(0)  xor DataOut(3)  xor DataOut(4)  xor
                             DataOut(7)  xor DataOut(9)  xor DataOut(10) xor
                             DataOut(13) xor DataOut(15) xor DataOut(16) xor

Reason for this bug was an insufficiency in the test bench.
Due to the 32 bit implementation of VHDL integer variables (simulator dependent though), 
only the EDAC's up to 24 bit are fully covered by the test bench.

The TEST BENCH WAS FIXED in Nov. 2002 by Sandi Habinc.
Instead of counting with a 32 bit loop variable, simulation is now done over
a configurable number of iterations (generic parameter) using random data 
(it would be impossible to simulate a all cases of the 64-bit edac).
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