================= CAN Release Notes ================= ======================================================================================= 26 May 2008 ======================================================================================= The current release is 5.2.4, available as from 26-May-2008. This new release is based on version 5.1, and incorporates a significant clean-up of the code and documentation. Release 4.6 and 5.1 will no longer distributed. The major modifications are: * AMBA I/F - The AMBA interface has been adapted from old 4.6 to current version (based on v5.1). - Latches in the AMBA interface were replaced by registers (in HurriAMBA.vhd) - The HurriAMBA testbench (HurriAMBA_tb.vhd) has been revised and debugged. * CAN Core - The source code has been revised, unused signals removed, and comments have been added. - Some entity and signal names have been updated, for a clearer nomenclature. - Synchronisation of Resets has been removed (in Synchro.vhd). - 'test' signal/port has been removed (in CANCore.vhd and Synchro.vhd). - Sync_bit.vhd file has been removed. The syncbit signal is still generated inside CANCore.vhd as a combinational statement. - mux_test_neg.vhd has been removed. The functionality it provided is now inside CANCore.vhd as a combinational statement. - A new testbench is provided for the CANCore block. - Simulation and synthesis scripts and reports are now provided. - The updated version has been tested against the BOSCH TestBench. ======================================================================================= 12 August 2005 ======================================================================================= The current release is 5.1, available as from 12-August-2005 to licensed users. It incorporates the bugfixes mentioned below, and the testbench from 4.6 has been ported to 5.1. However NO DOCUMENTATION EXISTS FOR 5.1. Any documentation applies to release 4.6 It seems in particular that the interpretation of the constants ps1, ps2, rsj has slightly changed from 4.6 to 5.1, making the description given in the 4.6 datasheet non-applicable for 5.1. Users should carefully evaluate their settings. ----------------------------------------------------------------------------- Due to the lack of documentation for the 5.1 version, and as the amba interface (HurryAMBA.vhd) is adapted to the 4.6 version, both versions are distributed, for the sake of completeness. FT, 27-Jun-2005 ----------------------------------------------------------------------------- A structural schematic of HurriCANe and applicability of testbenches to versions is illustrated in the file HurriCANeHierarchy.png ----------------------------------------------------------------------------- A VHDL coverage report is now provided with the code, and an encrypted simulation model is provided for download. ----------------------------------------------------------------------------- Comments from users/Undocumented Features: =========================================== ======================================================================================= Francisco Tortosa -- 19 May 05 -- HurriCANe_5.1 & TestBench Adapted 4.6 Testbench to Hurricane_5.0/5.1 Some bugs corrected to generate HurriCANe_5.1 ======================================================================================= cancoretb.vhd ------------- The testbench from the 4.6 version has been ported to the 5.0/5.1 version of the core, comprising the following changes/corrections (all modifications with respect to the old version are indicated in the file with: --ver5.1): - A delay is needed after every reset. 5.0 version takes some time before it considers the bus idle. - The clock signals were adapted. - Several bugs of the previous version of the testbench were corrected. - The previous version didn't wait for "intermission" after an error frame. - Bug detected in test EC2b, to be solved. Commented out test EC2b - Commented out the wrong test OF3 Other bugs: ---------- The points 1, 2 and 3 from the bug report dated 05 April 2004 (hereafter) were solved/corrected. Point 4 has been left unchanged because the functionality is not affected. ======================================================================================= 05 April 2004, 12 August 2005 ======================================================================================= BLOCK SYNCH_NEW.vhd (versions 5.x): ------------------------------ 1. inputs ps1, ps2, rsj and bpr: have default values assigned. These signals define the sample point to capture data and it is not fixed in the bit time. With these values the sample point varies and one bit is lost. Changing these values the whole frame sample is correct (although the sample point varies). ps1: 0101 changed to 1001 ps2: 1010 changed to 0101 Note from RW: default assignments in the port list are overridden by what is connected to those ports. In release 4.6, defaults have been changed through the hierarchy: ps1 is now 1010, and ps2 is 0101. ------------------------------ 2. duplicated 'edge' signal in the sensivity list of the process of the state machine ------------------------------ 3. confusing if clause: if sync_enable <= '1' then sync_enable_tmp <= '1'; ==> sync_enable will be always 1 After comparison with Aurelia's code (validated in ASIC and by Bosch testbench), this has been confirmed to be correct functionality. The confusing clause has been resolved to: sync_enable_tmp <= '1'; As this statement appears in the if and else branch, it could completely be moved out to the line 375 in v5.1). Note that both branches of the if/else are covered by the testbench. ------------------------------ 4. the next change of state: if hard_sync_enable ='1' and edge ='1' then next_state <= SYNC_state; counter_res <= '1'; does not change to SYNC_state as the following instruction (counter_res) provokes the change to the PS1_state. Note from RW: What is the conclusion? ------------------------------ BLOCK CAN_RX.vhd: The bit counter implemented starts in 1 with the SOF bit. The latest check of fields does not correspond to this count. The counter should start in 0 for the SOF bit or increment the bit number to extract the fields. ======================================================================================= 9 Feb 2004 ======================================================================================= Synthesis with Synopsys (DC/FPGA-Compiler) of the file crc_calc.vhd resulted in an elaboration error because a variable is used to infer flip-flops and read in the same process outside the "if rising_edge(clock)" section: Error: Tried to use a synchronized value(HDL-107) Fixed in release 4.6. ======================================================================================= Report from Francisco Tortosa Lopez, ESTEC, Oct 2003: ======================================================================================= A few issues have been found with HurriCANe Alpha 4.5 + Amba interface and fixed in 4.6 (updated HurryAMBA.vhd and HurryAMBA_tb.vhd): 1. Bit order of the transmitted and received messages identifier were inverted with respect to the CAN Standard. 2. The bits TXRM & TMRMR of the SETUP Register were confused. 3. There were some strange problems in the CWH State machine for transmission. I solved some issues and Mr Qiang Huang (jameshq@liverpool.ac.uk) who had been using this core as well and had experienced similar problems to mine apported his solution to improve this state machine. (Luca Stagnaro forwarded to me a message of him asking for support) --------------------------- Ah yes, about the documentation ... We found some errors (in the AMBA interface doc) HurrAMBA.pdf: page 3. SETUP Register: in first figure the following bits are missing 7: BPR1, 15: Disabled, 23: PS2_3, 31: RxClear (fixed in doc version 1.3 June 2005) The description of the bits TXRM and TMRMR should be improved ... ======================================================================================= Report received 16-Jan-2003: ======================================================================================= Concerning documentation (HurrAMBA.pdf), on page 8 the description of "trigger match register" seems equal to the description of "Error counter register" on page 7! (fixed in doc version 1.3 June 2005)