Synthesizable IP-Cores Available from ESA

Slides from the IP-Core Workshop held on 15th of June 2005

The following ESA cores are currently available or planned.

Name	Description	Status/Notes	Area
LEON2FT	The LEON2FT is the SEU fault tolerant version of the LEON2 processor. Flip-flops are protected by Triple Modular Redundancy and all internal and external memories are protected by EDAC or parity bits. Special licence restrictions apply to this IP (more information on request).	Release 1.0.9.7, 06-January-2005,tool compatilbility issues.	LEON2FT area
EVI32	The EVI32 is a 32-bit VME interface circuit designated to interface the ERC32 processor chip set to the VMEbus. The EVI32 fully adheres to the IEEE 1014-1987 VMEbus standard, and is compatible with the commercial VMEbus specification. EVI32 can act as a system controller and provides both master and slave interfaces. It has been implemented as a synthesizable VHDL model.	available evi32 notes	area
CUC CTM	The CCSDS Unsegmented Code (CUC) synthesizable VHDL core provides basic time keeping functions such an Elapsed Time counter according to the CCSDS Unsegmented Code specification. It provides support for setting, sampling and correlating the ET counter. It also comprises afrequency synthesizer with which a binary frequency is generated to drive the Elapsed Time counter. The CCSDS Time Manager (CTM) synthesizable VHDL core provides additional time services based on the Elapsed Time counter implemented in the embedded CCSDS Unsegmented Code (CUC) synthesizable VHDL core. The CCSDS Time Manager (CTM) core is interfaced as an AMBA APB slave.	available ctm notes	CTM Area on Xilinx Virtex-E 1200 LUT, 764 DFF, 2 ext. I/O
OBDH	The DOCC (DHS On-board Communication Controller) core features Control and Remote Terminal (CT/RT) functionality for OBDH (On-board Data Handling), DHS (Data Handling System, PSS-04-255) and RTU-kernel.	available obdh notes	Actel RT54SX72S: 1344 (comb.) 541 (sequential)
PTME	The core comprises a completeCCSDS packet telemetry encoder: Virtual Channel Assemblers, associated to various input interfaces (Packet-APB, Packet-Wire, Packet-Asynchronous-RS232 and Packet-Parallel), a Virtual Channel Multiplexer, and a telemetry encoder chain, including Turbo and Reed-Solomon encoder, and Convolutional encoder. The core is highly configurable at compile (synthesis) time and at runtime, and it is extensively documented (V0.7 R2 September 2005). The PTME is foreseen with a wrapper, connecting it to the AMBA AHB and APB on-chip buses (details and an example of configuration (R7 April 2004)). Tests performed on the AMBA interfaces are reported in the Validation Report	available PTME notes	PTME area
VCA, VCM, TCE	The separate IP's for Virtual Channel Assembler (VCA), Virtual Channel Multiplexer (VCM) and the Telemetry Channel Encoders (Reed-Solomon, Convolutional and Turbo Encoder) have been merged into - and are superseded by PTME	discontinued	unknown
CAN	The HurriCANe is a VHDL core comprising the following elements: CAN core, AMBA APB wrapper (to integrate the CAN core into a system-on-chip), and testbenches. An encrypted Modelsim (5.8a) model is available for evaluation.	Release 5.1, 12-Aug-2005, can notes	area
EDAC	Error Detection And Correction (EDAC) Encoders/Decoders are frequently used for protecting data in aerospace applications. The provided encoders/decoders support data widths from 4 to 64 bits, providing Single Error Correction and Double Error Detection, and in some cases Double Error Correction and Single Bank-error Detection. An encrypted Modelsim (5.8a) model is available for evaluation.	available version 0.6 August 2005 edac notes	area
PTCD	The design of the MA28140 chip (GEC-Plessey Semiconductors) has been ported to a synthesizable VHDL core implementing a complete CCSDS packet telecommand decoder, connected to the AMBA AHB and APB on-chip buses. The underlying TM/TC functionality is described in the data sheet of the MA28140 from GEC-Plessey Semiconductors with minor modifications. The license will be limited to developments that are funded by the European Space Agency.	available ptcd notes	Area on Xilinx Virtex-E 3500 LUT, 1000 DFF, 37 ext. I/O
PDEC	Synthesizable VHDL core comprising: a complete CCSDS packet telecommand decoder (PDEC3), a Command Pulse Distribution Module (CPDM) and a Command Pulse Distribution Selector (CSEL), all of them being integrated in an AMBA AHB wrapper. The IP is part of the Single Chip Telemetry and Telecommand ASIC that is currently being developed and validated by Saab Ericsson Space under ESA contract. The functionality of PDEC3, CPDM and CSEL is described in the User's Manual of the SCTMTC ASIC (Issue 11, March 2006). VHDL testbenches for this IP are available. The license will be limited to developments that are funded by the European Space Agency.	available	area
WIC	Wavelet Image Compression (lossy and lossless), VHDL core based on the Ocapi Flexwave IP developed by IMEC. Flexwave Documentation Package The license will be limited to developments that are funded by the European Space Agency.	wic (flexwave) notes	wic (flexwave) area
IP1553	A Mil-Std-1553 interface will be available for ESA internal use only. It can eventually be licensed directly from Astrium SAS, Velizy, France (contact Marc Souyri).	n/a	Area on Xilinx Virtex-E 2000 LUT, 500 DFF, 18 ext. I/O
SPW-AMBA	A synthesizable VHDL core implementing the SpaceWire Encoder/Decoder with FIFOs (for Xilinx Virtex-E technology) and AMBA AHB master/slave interfaces. Version V02 Architectural Specification and User Manual. Beta version (v00) can be downloaded as encrypted Modelsim (5.6e) objects for evaluation purposes.	available spacewiramba notes	spacewiramba area
SPWb	Synthesizable VHDL core implementing the SpaceWire Codec (including testbenches). Several documents are available: User Manual (22-Dec-2005), RTL Verification, Testbench User Manual.	available Release 2.0, 22-Dec-2005 uodspacewire notes	area