Public information related to VHDL.
ECSS Q60-02A ASIC/FPGA Development Standard
In a joint initiative between ESA, Tesat and the European Cooperation for Space Standardisation (ECSS), and with participation from reviewers in European industry, an ASIC/FPGA Development Standard has been elaborated and published on 17th of July 2007. As legacy version used in ongoing developments, the Final Draft (February 2004) is made available at this site.
The SEUs Simulation Tool (SST), Version 1.3, July 2004
SST page at University Antonio de Nebrija, containing release 2.0 from Nov. 2006
A set of Perl and tcl scripts, which allows injecting SEU like faults into HDL and netlist simulations. The Design Under Test (DUT) is analyzed, and a list of nodes is provided to the user. After user selection of a fault scenario, appropriate TCL force commands are generated for the modelsim simulator, which will then upset selected nodes of the design at the selected time during simulation. Author Daniel Gonzalez Gutierrez. The tool is provided for free download under GPL licence. However, if you download and use this tool, please inform us by sending a mail to IpCoreRequest[ampersand]esa.int and provide feedback/bugfixes to this same address.
and Manufacturing Requirements
(Format: Adobe PDF)
This document is used for ESA technology development contracts to minimise development risks and avoid "unpleasant surprises" late in the development. This document forms one part of the inputs to the ECSS-Q-60-02 standard for ASIC development, which is currently under preparation.
and Assurance Requirements
(Format: Adobe PDF)
This document represents the precursor of a specification of the same scope and objectives intended for issue within the ESA Procedures, Specifications and Standards, branch of Product Assurance and Safety (PSS-01 series). It establishes the basic requirements for the development of ASIC components, ASIC specific quality assurance requirements, prototype manufacture, testing and validation which are to be applied by ESA contractors and subcontractors. This document is referenced and complemented by the ASIC Design and Manufacturing Requirements . Author: Ralf de Marino.The Use Of FPGA In Space
Notwithstanding to the general methodology and recommendations outlined in the documents above, mostly applicable also to FPGA, specific considerations apply to the use of FPGA in space.
Last edited 08 August 2007